Hitachi, Ltd.

Director-general of the Agency of Industrial Science and Technology

Toru Toyabe

Sigeo Ihara

Tohru Nakamura

Kozo Katayama

Minoru Nagata

Takahiro Okabe

Shiroo Kamohara

Shuichi Yamamoto

Kiyoo Itoh

Hiromasa Noda

Tomoyuki Watanabe

Isao Yoshida

Kenji Kaneko

Yutaka Okada

Yokichi Itoh

Takeaki Okabe

Shin'ichiro Kimura

Junko Tanaka

Mineo Katsueda

Shikayuki Ochi

Masatomo Furumi

Yasushi Gotoh

Kikuo Watanabe

Hidefumi Itoh

Yukio Shirota

An interband single-electron tunnel/transistor utilizes an interband single-electron tunneling phenomenon between a valence band and a conduction band through a p-n junction. The transistor includes the combination of microcapacities as fundamental constituent elements each formed by joining a p-type semiconductor material doped with an impurity in the degree of concentration with which a Fermi level overlaps a valence band and an n-type semiconductor material doped with an impurity in the degree of concentration with which the Fermi level overlaps a conduction band. The microcapacity includes a p-n junction having a junction area with which interband electron tunneling is inhibited due to Coulomb blockade.

Interband single-electron tunnel transistor and integrated circuit

A finely structured grooved gate transistor of which the threshold voltage does not decrease in spite of the small size and of which the threshold voltage of the transistor can be adjusted by shape. The shape of a groove corner of the transistor as a semiconductor device is contained in a concentric circle having a radius of curvature r.+-.L/5 (L: channel length) and the radius of curvature r, i.e., the geometric parameter has a relationship with the doping concentration as shown in FIG. 1B. Alternatively, the average (a+b)/2 (geometric parameter) of the sum of the two sides opposite the right angle of a right triangle formed of a straight line in contact with the gate bottom in parallel to the substrate surface of a grooved gate transistor, a perpendicular line to the substrate bottom surface from the source and drain ends at a portion formed with a channel and a straight line in contact with the groove corner has a relationship with the doping concentration as shown in FIG. 1B. The threshold voltage is not reduced even when the channel length is decreased by adjusting the groove shape and the doping concentration.

Grooved gate transistor having source and drain diffused layers with

An interband single-electron tunnel transistor utilizes an interband single-electron tunneling phenomenon between a valence band and a conduction band through a p-n junction. The transistor includes the combination of microcapacities as fundamental constituent elements each formed by joining a p-type semiconductor material doped with an impurity in the degree of concentration with which a Fermi level overlaps a valence band and an n-type semiconductor material doped with an impurity in the degree of concentration with which the Fermi level overlaps a conduction band. The microcapacity includes a p-n junction having a junction area with which interband electron tunneling is inhibited due to Coulomb blockade.

A radiation-hardened semiconductor device including a bipolar transistor is disclosed in which a highly-doped layer equal in conductivity type to and larger in impurity concentration than the base region of the transistor is formed in that portion of the surface of the base region which exists beneath an insulating film, to prevent minority carriers injected into the base region, from reaching the above-mentioned surface portion. Thus, the injected minority carriers can reach a collector region without being extinguished by the recombination at the surface of the base region.

Radiation-hardened semiconductor device with surface layer

An I.sup.2 L type nonvolatile memory of this invention has a structure wherein a floating gate is disposed through an insulating film on the surface of a semiconductor layer in the vicinity of a base region of an NPN transistor in an I.sup.2 L. The I.sup.2 L type nonvolatile memory of this invention controls current to flow through the base region of the NPN transistor of the I.sup.2 L, by means of charges to be stored in the floating gate. That is, the collector output current of the NPN transistor of the I.sup.2 L is modulated in dependence on the presence or absence of a channel underneath the floating gate as is generated depending on the presence or absence of charges within the floating gate and the polarity of the charges. As a result, the variation of the base current appears as an output signal at a collector terminal of the NPN transistor of the I.sup.2 L, and data stored in the floating gate can be read out.

I.sup.2 L Memory with nonvolatile storage

In an insulated gate field effect transistor having a source region and a drain region of the P-conductivity type which are disposed in surface portions of a semiconductor substrate of the N-conductivity type in a manner to be spaced apart from each other, a gate electrode being disposed through an insulating film on the substrate between the source region and the drain region, an insulated gate field effect transistor wherein said drain region is disposed apart from said gate electrode, two regions of an intermediate region and a high resistance region which are of the P-conductivity type and which successively extend from said drain region towards the side of said gate electrode are disposed in surface portions of the substrate situated between said drain region and said gate electrode, said intermediate region having an impurity concentration lower than that of said drain region, said high resistance region having an impurity concentration lower than that of said intermediate region, and a source electrode extends over and beyond said gate electrode and said high resistance region through said insulating film and terminates over said intermediate region.

Insulated gate field effect transistor with source field shield

Growing community of inventors

Kokubunji, Japan

Toru Toyabe