Micron Technology Incorporated

Kabushiki Kaisha Toshiba

Intel Corporation

Lodestar Licensing Group LLC

Kabushiki Kaishi Toshiba

Toru Tanzawa

Tomoharu Tanaka

Shigeru Atsumi

Tadayuki Taura

Takashi Mori

Yoshinori Takano

Koji Sakui

Ken Takeuchi

Han Zhao

Hitoshi Shiga

Akira Goda

Riichiro Shirota

Shigekazu Yamada

Noboru Shibata

Haitao Liu

Yoshiyuki Tanaka

Krishna Kumar Parat

Kazunori Ohuchi

Takeshi Miyaba

Aaron S Yip

Tetsuo Endoh

Seiichi Aritome

Akira Umezawa

Masao Kuriyama

Susumu Shuto

Gertjan Hemink

Aurelio Giancarlo Mauri

Pranav Kalavade

Jeremy Binfet

Shantanu R Rajwade

Mark A Hawes

Qiang Tang

Ramin Ghodsi

Masanobu Saito

Deepak Thimmegowda

Tamotsu Murakoshi

Hiroshi Watanabe

Koichi Kawai

Naoki Yasuda

Toshio Yamamura

Ali Feiz Zarrin Ghalam

Akira Toriumi

Satoru Tamada

Peter B Harrington

Tetsuji Manabe

Seiichi Mori

Kentaro Watanabe

Yasuhiko Honda

Seiji Yamada

Shinji Satoh

Hiroyuki Sanda

Aurielo Giancarlo Mauri

Methods of forming a transistor might include removing portions of a semiconductor to define a semiconductor fin having an upper portion having an uppermost surface at a first level and extending from the first level to a second level, and a lower portion, wider than the upper portion, having an uppermost surface at the second level and extending from the second level to a third level; forming first and second isolation regions at the third level and adjacent the lower portion of the semiconductor fin; forming a first dielectric overlying portions of the semiconductor that are lower than a level between the first level and the second level; forming a second dielectric overlying an exposed portion of the upper portion of the semiconductor fin; forming a conductor overlying the second dielectric; and forming first and second source/drains in the lower portion of the semiconductor fin at the second level.

Field effect transistors having a fin

Apparatuses and methods for interconnections for 3D memory are provided. One example apparatus can include a stack of materials including a plurality of pairs of materials, each pair of materials including a conductive line formed over an insulation material. The stack of materials has a stair step structure formed at one edge extending in a first direction. Each stair step includes one of the pairs of materials. A first interconnection is coupled to the conductive line of a stair step, the first interconnection extending in a second direction substantially perpendicular to a first surface of the stair step.

Interconnections for 3D memory

Embodiments are provided that include a memory device having a memory array including a plurality of access lines and data lines. The memory device further includes a circuit coupled to the plurality of access lines and configured to provide consecutive pulses to a selected one of the plurality of access lines. Each pulse of the consecutive pulses includes a first voltage and a second voltage. The first voltage is greater in magnitude than the second voltage, and the first voltage is applied for a shorter duration than the second voltage.

Random telegraph signal noise reduction scheme for semiconductor memories

Apparatus might include an array of memory cells and a controller to perform access operations on the array of memory cells. The controller might be configured to establish a negative potential in a body of a memory cell of the array of memory cells, and initiate a sensing operation on the memory cell while the body of the memory cell has the negative potential. Apparatus might further include an array of memory cells, a timer, and a controller to perform access operations on the array of memory cells. The controller might be configured to advance the timer, and establish a negative potential in a body of a memory cell of the array of memory cells in response to a value of the timer having a desired value.

Apparatus for establishing a negative body potential in a memory cell

Apparatuses and methods for performing concurrent memory access operations for multiple memory planes are disclosed herein. An example method may include receiving first and second command and address pairs associated with first and second plane, respectively, of a memory. The method may further include, responsive to receiving the first and second command and address pairs, providing a first and second read voltages based on first and second page type determined from the first and second command and address pair. The method may further include configuring a first GAL decoder circuit to provide one of the first read voltage or a pass voltage on each GAL of a first GAL bus. The method may further include configuring a second GAL decoder circuit to provide one of the second read level voltage signal or the pass voltage signal on each GAL of a second GAL bus coupled to the second memory plane.

Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operation

Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one access line of at least one memory cell and at least one source, channel and/or drain of at least one peripheral transistor, such as one used in an access line decoder circuit or a data line multiplexing circuit. The apparatus can also include a number of pillars of a second semiconductor material extending through the tiers of the first semiconductor material, each pillar including either a source, channel and/or drain of at least one of the memory cells, or a gate of at least one of the peripheral transistors. Methods of forming such apparatus are also described, along with other embodiments.

Semiconductor apparatus with multiple tiers, and methods

A semiconductor device structure comprises stacked tiers each comprising a conductive structure and an insulating structure longitudinally adjacent the at least one conductive structure, at least one staircase structure having steps comprising lateral ends of the stacked tiers, and an opening laterally adjacent a first side of the at least one staircase structure and extending through the stacked tiers and continuously across an entire length of the at least one staircase structure. Conductive structures of the stacked tiers laterally extend from the steps of the at least one staircase structure completely across a second side of the at least one staircase structure opposing the first side to form continuous conductive paths laterally extending completely across the stacked tiers. Additional semiconductor device structures, methods of forming semiconductor device structures, and electronic systems are also described.

Devices including staircase structures, and related memory devices and electronic systems

Transistors might include first and second semiconductor fins, a first source/drain region in the first semiconductor fin and extending downward from an uppermost surface of the first semiconductor fin, a second source/drain region in the second semiconductor fin and extending downward from an uppermost surface of the second semiconductor fin, a dielectric between the first and second semiconductor fins and adjacent to sidewalls of the first and second semiconductor fins, and a control gate over the dielectric and between the first and second semiconductor fins and extending to a level below upper surfaces of the first and second source/drain regions.

Some embodiments include apparatuses and methods of using such apparatuses. One of the apparatuses includes a semiconductor material, a pillar extending through the semiconductor material, a select gate located along a first portion of the pillar, memory cells located along a second portion of the pillar, and transistors coupled to the select gate through a portion of the semiconductor material. The transistors include sources and drains formed from portions of the semiconductor material. The transistors include gates that are electrically uncoupled to each other.

Memory device including pass transistors in memory tiers

Some embodiments include apparatuses and methods having a substrate, a memory cell string including a body, a select gate located in a level of the apparatus and along a portion of the body, and control gates located in other levels of the apparatus and along other respective portions of the body. At least one of such apparatuses includes a conductive connection coupling the select gate or one of the control gates to a component (e.g., transistor) in the substrate. The connection can include a portion going through a portion of at least one of the control gates.

Memory array having connections going through control gates

Some embodiments include apparatuses, and methods of forming and operating the apparatuses. Some of the apparatuses include a conductive line, non-volatile memory cells of a first memory cell type, the non-volatile memory cells coupled in series among each other, and an additional non-volatile memory cell of a second memory cell type coupled to the conductive line and coupled in series with the non-volatile memory cells of the first memory cell type. The second memory cell type is different from the first memory cell type.

Memory device including mixed non-volatile memory cell types

Apparatuses and methods involving accessing distributed sub-blocks of memory cells are described. In one such method, distributed sub-blocks of memory cells in a memory array are enabled to be accessed at the same time. Additional embodiments are described.

Apparatuses and methods involving accessing distributed sub-blocks of memory cells

Some embodiments include apparatuses and methods having a conductive line, a memory cell string including memory cells located in different levels the apparatus, and a select circuit including a select transistor and a coupling component coupled between the conductive line and the memory cell string. Other embodiments including additional apparatuses and methods are described.

Memory having memory cell string and coupling components

Growing community of inventors

Tokyo, Japan

Toru Tanzawa