Nec Corporation

Toru Takamichi

Masahiro Shigihara

Satoshi Kamiya

Tutomu Murase

Daisaku Ogasahara

Shinsuke Fujisawa

An optical signal generation unit () generates an optical signal for transmission by adding modulation based on a driving signal to a carrier wave. A filtering unit () performs a filtering process on the driving signal. The filtering unit () may perform time domain equalization, and may perform frequency domain equalization. Specifically, the filtering unit () performs a filtering process on the driving signal, and thus sets a peak value of a power spectral density of the optical signal for transmission to be equal to or less than a second reference value while an integrated value obtained by integrating the power spectral density of the optical signal for transmission in a frequency direction is maintained at equal to or greater than a first reference value.

Light transmission apparatus, light communication system, light reception apparatus, method for adjusting light transmission, method for transmitting light, and method for receiving light

A multiplexing apparatus stores fixed length data into which information signals supplied from channels are divided; determines an output channel by selecting the each channel cyclically; acquires the fixed length data from the output channel based on a channel multiplexing ratio number to store the fixed length data in a payload in turn; adds assignment information to the payload; and creates a multiplexing frame by using the payload to transmit to a transmission channel. A demultiplexing apparatus detects the assignment information from the payload of the multiplexing frame received to the transmission channel; creates distribution information for distributing the fixed length data to each channel based on the assignment information; detects the fixed length data from the payload to distribute the fixed length data to each channel based on the distribution information; and couples the fixed length data to reproduce the information signal.

Multiplexing transmission system, multiplexing apparatus, demultiplexing apparatus and a multiplexing transmission system

A cyclic code processing circuit, network interface card, and method for calculating a remainder from input data comprising a plurality of bits arranged in parallel. The calculation is performed by first computing a first remainder obtained by dividing an integral multiple data block by a generator polynomial, the integral multiple data block comprising a plurality of words that precede the final word of the input data. Then, a second remainder is computed by dividing the final word by the generator polynomial, the final word comprising the parallel bits located at the end of the input data. The input data remainder is calculated using the first and the second previously calculated remainders.

Cyclic code processing circuit, network interface card, and cyclic code processing method

To eliminate the need for buffering in order to calculate data length information on data as an object of computation, a first exclusive-OR unitexecutes computation of exclusive-OR of a cyclic code R(x) of the integral multiple bit bits block A(x) and a data string of M bits, containing the fraction bits block B(x). A first shifting unitshifts the exclusive-OR of the cyclic code R(x) and the data string of M bits, containing the fraction bits block B(x), by {M&#x2212;H(k)} bits toward a least significant side, where M is a parallel width and H(k) is a bit length of the fraction bits block B(x). An R'(x) generation unitgenerates a cyclic code R&#x2032;(x) that is a cyclic code of the data after shifting. To obtain R&#x2033;(x), a second shifting unitshifts the cyclic code R(x) by H(k) bits toward a most significant side. A second exclusive-OR unitexecutes computation of exclusive-OR of the cyclic code R&#x2032;(x) and data R&#x2033;(x).

Parallel cyclic code generation device and parallel cyclic code error detection device

An alarm transfer method for use in a wide area Ethernet network has the steps of generating a plurality of fixed-length frames from an Ethernet frame sent from a client terminal, generating capsules each comprised of each of the fixed-length frames, a type field for notifying a fault, a forward relay line fault notification field for notifying a fault in a forward direction, and a backward relay line fault notification field for notifying the fault in a backward direction, multiplexing the capsules to generate a frame which is transferred to an Ethernet network, and demultiplexing capsules from a received frame to recognize a fault for each Ethernet path.

Alarm transfer method and wide area Ethernet network

An STM mapping circuit is disclosed having a configuration that includes: a packet length detection circuit for generating byte effectiveness information that indicates whether byte data are effective data or not; routing circuits for generating routing information for rearranging byte data in a prescribed order while using byte effectiveness information to eliminate pad bytes; packet filter circuits for taking in packet data for each logical channel in accordance with channel number signals that indicate which logical channel the packet data belong to; M&#xd7;M switches for sorting packet data for logical channel in a prescribed order while removing pad bytes in accordance with routing information; and packet memories that hold, for each logical channel, packet data that have been sorted by the M&#xd7;M switches.

STM mapping circuit and method

A path memory for a Viterbi decoder stores 2 path select command signals generated a T interval earlier than reference clock timing. In response to a path select command signal that is generated at the reference clock timing corresponding to each of the 2 rows, one of the stored path select command signals which correspond to two possible states of a 2T interval earlier than the reference clock timing and are separated from each other by a distance of 2 rows, is selected for each row. A matrix array of memory cells are arranged in the 2 rows. To achieve low power consumption, the memory, cells are divided into a first array of odd-numbered columns and a second array of even-numbered columns. Each row of the first-array memory cells is responsive to the row-corresponding path select command signal and the selected path select command signal for selecting one of four possible states latched in the memory cells of preceding odd-numbered columns a 2T interval earlier than the reference clock timing, and each row of the second-array memory cells is responsive to the row-corresponding path select command signal and the selected path select command signal for selecting one of four possible states latched in the memory cells of preceding even-numbered columns a 2T interval earlier than the reference clock timing. The first and second arrays alternately operate at 2T-intervals.

Low power path memory for viterbi decoders

An ATM concentrator connects (m&times;n) input highways to n output highways and performs a full priority control. The ATM concentrator has output cell buffers for respective quality classes. Cells are read from the output buffers of the quality classes and the number of valid cells thereof is checked. A quality class c is determined with respect to which an accumulated value of the numbers of valid cells calculated successively from quality classes of higher priority is maximum within the total number of the output highways. The ATM concentrator outputs only cells of the highest priority class if the quality class c is the highest priority class. When the quality class c is not the highest priority class, the ATM concentrator writes valid cells of next priority class through the quality class c over cells that are not valid cells in the highest priority class.

Traffic priority control system for a concentration-type ATM switch

A BRM changing circuit 4 that changes congestion information of a BRM cell is disposed on the output side of a down line (from the network side to the user side) of a cell rate supervising apparatus. The BRM changing circuit 4 places an ACR value calculated by an ACR calculating circuit 3 with congestion information (a CI bit, an NI bit, and an ER area) in a BRM cell received from the network through the down line to the ER area of the BRM cell. The resultant BRM cell that has been changed by the BRM changing circuit 4 is sent to the user side terminal unit through the down line.

Cell rate supervising apparatus

There is provided a fault self-supervising system of cell processor to execute fault supervising for internal circuit in the cell processor during the in-service period while the ordinary operation of the cell processor is kept without giving any influence on the main signal cell flow in the cell processor of the ATM network. In the structure of the fault self-supervising system of cell processor, the cell such as control cell or idle cell in the ATM cell flow which is not processed in the cell processor is overwritten by the supervising cell having a combination of VPI and VCI which is not used in the cell process and it is then applied in the preceding stage of the arithmetic circuit as the supervising object an is then transferred within the arithmetic circuit, the supervising information signal CHK indicating the operating condition of the arithmetic circuit obtained as a result of the transfer is compared and collated with the expected value E, a defective circuit of arithmetic circuit is detected from matching/mismatching as a result of comparison and the supervising cell is extracted in the subsequent stage of the arithmetic circuit.

Fault self-supervising system of cell processor

The invention provides a dynamic traffic shaping apparatus which allows dynamic shaping processing wherein the shaping cell rate is varied dynamically in response to a rate variation of a terminal acquired from a network. The dynamic traffic shaping apparatus includes a rate information processing section for predicting a sending rate of a transmission terminal in response to rate control information detected from a cell directed from a reception terminal side toward a transmission terminal side and successively storing the sending rate in an updating manner as sending rate information of an arrival cell for each virtual path and each virtual channel. The cell stored in a cell buffer for temporarily storing an arrival cell arriving from the transmission terminal side for each virtual path and each virtual channel is read out at an interval based on the sending rate information stored in the rate information processing section corresponding to the virtual path and the virtual channel and is sent out to the reception terminal side by a read control section.

Dynamic shaping apparatus of traffic of ATM network

In a cell rate supervising system for supervising a rate of cells flowing in a certain direction, a binary mode congestion feedback loop terminating unit terminates a first congestion feedback loop on a downstream side of that direction. The first congestion feedback loop receives a first congestion management cell from the downstream side and turns it in a binary mode to the downstream side. Also, an explicit rate (ER) mode congestion feedback loop terminating unit is provided on an upstream side of the binary mode congestion feedback loop terminating unit, and terminates a second congestion loop on an upstream side of the direction. The second congestion feedback loop receives a second congestion management cell from the upstream side and turns it in an ER mode to the upstream side. Further, a dynamic generic cell rate algorithm unit is provided on an upstream side of the ER mode congestion feedback loop terminating unit, and monitors the rate of cells in accordance with the second congestion management cell.

Growing community of inventors

Tokyo, Japan

Toru Takamichi