Fujitsu Corporation

Toru Takaishi

Tetsu Tanizawa

An oscillating circuit 30 outputs a signal .o slashed..sub.o whose pulse cycle T is a linear function T=kS+m of a control input value S. A frequency control circuit 10, every time a counter 11 counts a number Nr of pulses of a reference signal .o slashed..sub.r, calculates S=No-m/k, where No is a count of .o slashed..sub.o counted by the counter 12, makes a judgement on convergence of .o slashed..sub.o based upon the difference between input and output values of a register 14, makes the register 14 hold S, updates Nr=S+m/k and clears the counter 12 to 0. A digital phase control circuit 20 judges a advance/delay of the phase of .o slashed..sub.o relative to .o slashed..sub.r with a phase comparator circuit 21, decrements/increments a count with a counter circuit 22 every time a judgement on the advance/delay of the phase is made and when the result of the judgement on the advance/delay of the phase is reversed from the previous result of that, changes the count to a value that is half the number of times that the same judgement was made successively before the reversal.

Digital frequency control circuit phase control circuit and PLL circuit

The present invention is to provide an output circuit, for a semiconductor circuit, capable of increasing the rise or fall time of an output signal without reducing the operating frequency of the output circuit, and thus effectively preventing occurrence of a malfunction due to an undesired change in the output signal caused by ringing, noise, or reflection occurring at the transition of the output signal. In the structure of present invention, an output circuit for a semiconductor circuit includes an input circuit, an output circuit including a transistor, and a control signal control circuit that lies between the input circuit and output circuit, outputs a control signal for use in driving the transistor in the output circuit, and changes the control signal according to a function of time.

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Kawasaki, Japan

Toru Takaishi