Tektronix International Sales Gmbh

Calsonic Kansei Corporation

Toru Takai

Hiroshi Komatsu

Minoru Tsuchiya

Hisao Takahashi

Ryoichi Sakai

Susan C Adam

Hideaki Okuda

Toshio Sugiyama

Kazumasa Ito

Takayuki Hayase

Fujihiko Omiya

Sachio Koyama

Koichi Iwasaka

Tsutomu Kawada

Takumi Funatsu

Instinctive operation of editing parameters of waveform is provided. Tabsandare displayed on a display screento show existence of parameter edit screen layers of different combinations of characters, waveforms and channels. If one of the tabs are selected the display is switched to show the corresponding parameter edit screen layer. Channel characters or waveforms are displayed on the tabsandand are changed dynamically according to the setting so that a user can easily realize setting outlines of the respective channels at a glance.

Signal generator display interface for instinctive operation of editing waveform parameters

A pulse delay circuit induces lager jitter to faster input reference pulse trains than before. A buffer receives a reference pulse train and provides non-inverted and inverted pulses. Low pass filters (LPF) and comparators receive the non-inverted and inverted pulses from the buffer and provide pulses having delayed leading and trailing edges. Dividers divide the delayed pulses by 2 to produce the respective pulse trains having a half frequency. An XOR gate produces an exclusive OR of the delayed and divided pulse trains to provide a pulse train having delayed leading and/or trailing edges relative to the reference pulse train. If the delays by the LPFs and comparators are changed, the output pulses from the XOR gate have jitter.

Widening jitter margin for faster input pulse

Delays induced to leading and trailing edges of an input pulse train are updated faster than before. First and second delay paths receive delay data for inducing delays to leading edges and/or trailing edges of an input pulse train. An OR circuit combines the outputs of the delay paths. First and second gates receive the input pulse train and selectively provide the input pulse train to the first and second delay paths independent of the edge position of the input pulse train. A delay time setup circuit generates a CTRL signal for controlling the first and second gates and the loading of the delay data to the first and second delay path. The CTRL signal causes the gates to selectively switch the input pulse train from one delay path to another while the delay data is selectively loaded in the delay path not receiving the input pulse train.

Variable delay circuit with faster delay data update

A jitter inducing circuit receives a reference pulse train and induces desired amounts of jitter to the rising and/or falling edges of the pulses. First and second delay blocksandalternately delay the selected edge or edges of the provided reference pulse train interval by preset delay times for every interval. A signal composercomposes the outputs of the first and second delay blocksand. A delay time setup circuit controls the delay times of the delay blocksand. The delay times may change for each interval as a function of time so as to trace a desired function such as a sinusoidal or triangular function.

Circuit and method for inducing jitter to a signal

Tanks are respectively structured such that seat plates are combined with tank main bodies, and the two end openings thereof are respectively closed by end plates. The direction in which the end plates are combined with the seat plate and tank main body is defined in an only-one-meaning manner in accordance with the engagement between engagement projecting pieces and engagement holes. The seat plates and end plate are respectively clad members structured such that brazing material is cladded only on the outer surface side of the tanks.

Aluminum-alloy heat exchanger

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Tokyo, Japan

Toru Takai