Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Toru Shiomi

Shigeki Ohbayashi

Atsushi Ohba

Kenji Anami

Tomohisa Wada

Kimio Ueda

Kunihiko Kozaru

Kakutaro Suda

Yoshito Nakaoka

Jun Takahashi

Tetsuo Higuchi

Yoshitsugu Dohi

To provide a semiconductor memory device that can be mounted on both sides of a circuit board having a relatively simple wiring pattern and can be manufactured at a low cost, the semiconductor memory chip of the present invention includes a plurality of memory cells, a control circuit formed on a semiconductor substrate, a plurality of electrode pads are formed on one of the principal planes for the purpose of input and output of signals to/from the control circuit, wherein at least a pair of the electrode pads consist of selective connection electrode pads that can drive the control circuit by selecting and connecting either one thereof, and the two selective connection electrode pads are disposed on both sides of a longitudinal or lateral chip centerline on the one principal plane.

Semiconductor memory chip and semiconductor memory device using the same

A power supply potential GNDP as a substrate potential of two N-channel MOS transistors constructing an SRAM transistor memory cell is enabled to be controlled independent of a ground potential GNDM as a source potential of the N-channel MOS transistors. In the case where a standby current failure occurs, by weakening the driving ability of the N-channel MOS transistors by a substrate effect, the failure can be found in a functional test. A defective memory cell as a cause of the standby current failure, in which a small leak occurs can be specified and is replaced by a redundant memory cell, thereby enabling the yield to be improved.

Semiconductor memory device capable of repairing small leak failure

A semiconductor integrated circuit identifies and salvages defective memory cells producing a dc current error, such as a standby current fault, and thereby improves semiconductor chip yield. During the wafer test stage of the manufacturing process, a positive and negative supply voltage are both applied to the two inverter circuits of the SRAM memory cell to detect defective memory cells where a microshort occurs. The fuse inserted the supply line of the detected defective memory cell is then broken to interrupt applying a positive or negative supply voltage to the defective memory cell, and a redundant memory cell provided in the memory cell array is substituted for the defective memory cell.

Semiconductor integrated circuit

In an input buffer circuit, a second stage includes a BiNMOS non-inverter and a CMOS inverter, and a driver circuit includes BiNMOS push-pull circuits.

Semiconductor integrated circuit device using BiCMOS technology

In a cache memory, when column address signals designating a defective column of a tag memory are input, a control circuit may inactivate the tag memory and control a switch circuit so that a spare data input/output terminal of a data memory is coupled to a data bus between the tag memory and a logic circuit. Compared to the conventional case in which a defective column of the tag memory is only replaceable by a spare column within the same tag memory, the degree of freedom in redundancy, and also the yield increase.

Semiconductor memory device capable of performing data reading/writing in units of plurality of bits

A pair of driving bipolar transistors of a lateral type T1 and T2 have emitters coupled to a ground potential, collectors connected to a pair of highly resistive elements R1 and R2. Highly resistive elements R1 and R2 have respective other ends coupled to power supply potential V.sub.CC, and bases and collectors of transistors T1 and T2 are cross-connected to each other, thereby forming a flipflop circuit. Access MOS transistors Q3 and Q4 having a gate potential controlled by word line WL are each connected to form a conduction path between one of storage nodes A and B and one of the pair of bit lines BL and /BL.

Static type semiconductor memory device capable of operating at a low

An improved output driver circuit for a semiconductor integrated circuit device, wherein a stepped control voltage generation circuit is connected to the gate of a driving transistor for driving an output terminal DQ. The stepped control voltage generation circuit responds to an applied input data signal to provide a stepped control voltage changing in a stepped form including a plurality of steps to the gate of the driving transistor. The driving transistor therefore changes its state on a step by step basis from a cut off state to a conduction state. Thus, sharp change in output current flowing through the output terminal can be prevented, and noise caused by a parasitic inductance can be avoided, thus preventing an erroneous operation in the device.

Output driver circuit for restraining generation of noise and

A level converting circuit comprises first and second complementary metal oxide semiconductor (CMOS) inverter circuits, and first and second N-Channel metal oxide semiconductor (NMOS) transistors. The first CMOS inverter circuit and the first transistor are connected in series between a relatively high power supply voltage and a relatively low power supply voltage. The second CMOS inverter circuit and the second NMOS transistor are connected in series between the relatively high power supply voltage and the relatively low power supply voltage. Complementary emitter coupled logic (ECL) level signals are converted into MOS level signals by the first and second CMOS inverter circuits. Current flow from the relatively high power supply voltage to the relatively low power supply voltage is inhibited by the first and second NMOS transistors. The level converting circuit can be used to interface a metal oxide semiconductor (MOS) memory cell array to a bipolar peripheral circuit.

Low power ECL/MOS level converting circuit and memory device and method

A divided word line driving circuit applicable to a static random access memory (SRAM) employing a divided word line method is disclosed. When a divided word line is activated, the potential at the input of an inverter for driving the word line is brought to a low level. When the input signals S1 and S2 are both at a low level, the divided word line is brought to an inactive state. The input of the inverter is charged by a transistor 101 in addition to a transistor 102 which is always on. In other words, transistor 101 contributes to accelerating charging of the input of the inverter. Consequently, the potential of the divided word line is made to rise at high speed, so that access operation at high speed can be achieved. The circuit is implemented with a small number of transistors, so that it becomes also possible to enhance the degree of integration of a SRAM.

Semiconductor memory device capable of driving divided word lines at

An input buffer circuit applicable as a BiCMOS RAM address buffer is disclosed. An improved level shift circuit 59 includes PMOS transistors 14 and 17 for bypassing emitter follower transistors 12 and 15, and NMOS transistors 13 and 16 for constituting a controllable current source Two differential amplifier circuits operating in response to an input signal having an ECL logic amplitude are provided, and emitter follower transistors 12 and 15 are driven by one of them, MOS transistors 13, 14, 16, and 17 are driven by the other. High operating speed is achieved under less current consumption, since emitter follower transistors 12 and 15, and MOS transistors 13, 14, 16, and 17 are driven, respectively.

BiCMOS input buffer circuit operable at high speed under less power

A self-timed random-access memory device includes randomly accessible memory circuitry (7), a clock generator (9) responsive to an external clock signal for generating an internal clock signal, an input circuit (8') responsive to the internal clock signal for latching and outputting a supplied input signal, an output circuit (11') responsive to the internal clock signal for latching and outputting an output from the memory device, and circuitry (81, 82, 85, 86; 115, 116, 124, 125; 135, 136, 144, 145) responsive to a through state specifying signal (TH, THM) for disabling the latch function of the input circuit and the output circuit. The memory device can be switched, in response to the through state specifying signal, between a mode operating synchronously with the externally supplied clock signal and another mode operating asynchronously with the externally supplied clock signal.

Semiconductor integrated circuit capable of synchronous and asynchronous

A bipolar RAM comprising a plurality of memory cells formed of cross-coupled bipolar transistors and a peripheral bipolar circuit formed of bipolar transistor, provided with an epitaxial layer which is to be the collector region of the bipolar transistor in the memory cell portion which is thinner and has higher impurity density than the epitaxial layer which is to be the collector region of a bipolar transistor in the peripheral circuit.

Bipolar cross-coupled memory cells having improved immunity to soft

A logic circuit includes an output pull up npn bipolar transistor (15; 28; 38), an output pull down pnp bipolar transistor (16; 29; 39), a first insulated gate type transistor (11, 12; 21, 22, 23, 24; 31, 32, 33, 34) for controlling the base potential of the output pull up bipolar transistor in response to an input signal, a second insulated gate type transistor (14; 25, 26, 27; 35, 36, 37) for controlling the base potential of the output pull down bipolar transistor in response to the input signal, and an impedance element (13; 18; 30; 40) for short-circuiting the base and the collector of the output pull down bipolar transistor. The impedance element is separated from the signal input terminal, and is formed by a resistance or an insulated gate type transistor operating in response to the base potential of the pull up transistor. The output pull up and pull down transistors both have collector grounded arrangement.

BiCMOS logic circuit using complementary bipolar transistors having

An address buffer decoder comprises n address buffer circuits, a decoder circuit, 2.sup.n level converting circuits and 2.sup.n driver circuits. Each of the address buffer circuits has an input terminal receiving an address signal of an ECL level. The decoder circuit comprises a plurality of output terminals and a plurality of inverted output terminals in each of the address buffer circuits and a plurality of interconnections. A selecting signal of an 'L' level is outputted to one of the plurality of interconnections depending on combinations of address signals inputted to the plurality of address buffer circuits. The selecting signal is converted into a signal of an MOS level by each of the level converting circuits. Current of the signal of the MOS level is amplified by each of the driver circuits. The signal of the MOS level is outputted to a corresponding selecting line.

Growing community of inventors

Hyogo, Japan

Toru Shiomi