Mitsubishi Denki Kabushiki Kaisha

Toru Shimizu

Masahito Matsuo

Toyohiko Yoshida

Shunichi Iwata

Ken Sakamura

Shigeo Mizugaki

Yuichi Saito

Tatsuya Enomoto

Toshio Doi

Yukari Watanabe

Katsumi Dosaka

Masaki Kumanoya

Yukihiko Shimazu

Yuichi Nakao

Akira Ohtsuka

Katsunori Sawai

Toshio Kishi

A data processor performs various types of EIT (exception, interrupt, trap) processing in connection with the execution of the preceding and following instructions in parallel. In one embodiment, an exception is detected resulting from processing the previous instruction in the pair being executed in parallel before completion of instruction processing where the exception requires re-execution. When the exception is detected a control means prevents the execution means from executing both preceding and following instructions. An additional feature is a control unit that controls when an interrupt is accepted during parallel execution. In another embodiment, a first decoder outputs suppressing information when the preceding instruction is a predetermined instruction having a possibility of causing a trap. A validity judgment circuit prevents the second decoded result from being issued when suppressing information is generated.

Data processing system capable of executing groups of instructions,

A a data processing system capable of returning correctly from an exceptional processing by the same processing as that in the case of executing instructions one by one without particular control even if an exception occurs in the midway of the instruction processing, and capable of selecting a mode for executing instructions one by one in debugging or a test, so that a plurality of instructions are executed in parallel with simple control.

Data processing system capable of executing groups of instructions in

An external bus I/F section has a function in which, when a bus access is requested by an instruction execution section, high-order several bits of a logical address generated by a CPU are outputted from an output terminal to the outside of a chip, as a space identifier for indicating which of an integrated ROM space, an integrated RAM space, and the external space is accessed by a currently executed program. A part of an address generated by the CPU is used so that the space which is accessed by the currently executed program is known from the outside in real time without requiring an external hardware.

Microcomputer for accessing a memory outside the chip by using an

Data processing system capable of execution of plural instructions in

A microcomputer which comprises a processor and a memory integrated on one chip wherein the memory is arranged in a plurality of memory cell region rows, and a processor is arranged between the memory cell region rows. A microcomputer wherein the memory cell regions are connected to each other row by row through a bus each of which is connected to the processor.

Microcomputer

A data processor being provided with a microdecoder which decodes instruction codes comprising two operation code parts, a source operand specifying part and a destination operand specifying part, wherein an optional bit area of source data (a register of a general register file or a memory) is inserted in an optional bit area (determined by the value of the first operation code part) of a destination register according to the decoding result, and an optional bit area (determined by the value of the second operation code part) of a source register is extracted and stored in an optional bit area of destination (a register of the general register file or the memory), thereby making it possible to 'process the insertion and extraction operations to and from optional byte positions of registers' at a high speed with short instruction code size.

Data processor and control circuit for inserting/extracting data to/from

This invention relates to a data processor with pipelining system, which is provided with at least two stages each having working stackpointers, and so constructed that each stage can independently refer to the working stackpointer corresponding to each stage, and the renewal of each working stackpointer corresponding to each stage occurs synchronously with pipeline processing, so that when execution of a plural instructions including designation of operands under stack-push addressing mode and stack-pop addressing mode, result of address calculation executed at the address calculation stage is sequentially transferred to a corresponding working stackpointer in a next pipeline stage. This is synchronized with the transfer of instructions through the stages of pipeline, thereby being possible for the data processor to smoothly execute pipelining process.

Multiple sequentially transferrable stackpointers in a data processor in

A shift circuit 213 used in arithmetic operations is provided with the shift width generating circuit 217 which generates a shift width data from lower bits of an access address and an access size, and a circuit is provided to generated data comprising the first select output circuit 214, the third select output circuit 216 and the like which generate a data by merging byte by byte selected from either an output of the shift circuit 213 or a value of a register of a register file 210 according to the combination of the lower bits of the access address and the access size. It is possible to align the data in the shift circuit 213 which is provided for the purpose of arithmetic operations, and exclusive alignment circuit is made unnecessary thereby enabling it to reduce the amount of hardware.

Data processor and read control circuit, write control circuit therefor

A data processor which is provided with a flag in a Processor Status Word (PSW) 116 for storing prohibiting/enabling status for receiving all of the interrupt requests, and in which the instruction execution control unit 114 controls so that the flag becomes in the enabling status when an interrupt request having a priority level is received and the flag becomes in the prohibiting status when an interrupt request having no priority level is received. Hence, for interrupt requests having priority levels, an interrupt request of high priority level can be received immediately without via the interrupt prohibiting status. For interrupt requests having priority levels, it becomes possible to receive an interrupt request of higher priority level without via the interrupt prohibiting status. For interrupt requests having no priority level such as for debugger and the like, it becomes unnecessary to perform a multi-interrupt processing.

Data processor with means for separately receiving and processing

A data processor, comprises: a microaddress input selector 252 which, when decoding an instruction code, generates a main microaddress signal 212 corresponding to an operation code part, a submicroaddress signal 218 corresponding to an addressing mode designating part and an address calculation request signal 233 indicating whether address calculation is necessary or not, and selects an address signal corresponding to an operation code part or to an addressing mode designating part responsive to the address calculation request signal 233; and an instruction execution control unit control circuit 256 which controls the microaddress input selector 252; and is capable of executing the instruction having the addressing mode designating part independent from the operation code, rapidly and with a small microprogram size.

Microprogram data processor processing operand address calculation and

A a data processing system capable of returning correctly from an exceptional processing by the same processing as that in the case of executing instructions one by one without particular control even if an exception occurs in the midway of the instruction processing, and capable of selecting a mode for executing instructions one by one in debugging or a test so that a plurality of instructions are executed in parallel with simple control.

Data processor capable of execution of plural instructions in parallel

A data processing system which is provided with a plurality of operation units and a function which executes a plurality of instructions in parallel by each of these plurality of operation units, respectively, wherein operation results executed by these plurality of operation units are reflected on flags which are included in a processor status word (PSW), thereby, those plurality of instructions are executed in parallel in the respective different operation units, and at that time, results of operation processing of the respective instructions are reflected on the flags included in the PSW, then, the flags can be updated by simple control, and the operation results executed by those plurality of operation units are reflected on the flags included in the PSW according to the order of execution of the instructions, thereby, those plurality of instructions are executed in parallel by the respective different operation units, and at that time, the results of operation processing of the respective instructions are reflected on the flags included in the PSW according to the order of execution of the instructions, whereby enabling to realize the high speed operation without providing such complicated processing as temporarily saving information for reflecting the results of operation processing on the flags until processing of the preceding instructions is finished.

System having status update controller for determining which one of

A method and apparatus for processing exceptions in a microprocessor having a plurality of pipelined stages. The method comprises the steps of generating an exception processing code at a given stage to indicate the occurrence of an exception at the given stage; temporarily stopping processing at the given stage; transferring the exception processing code to a special stage; decoding said exception processing code at the special stage; and causing the pipeline to execute exception processing when the exception processing code is decoded at the special stage. Using the invention, the microprocessor can avoid much of the delay and complexity resulting from using an external circuit to control exception processing and can cope with the occurrence of an exception at any stage without prematurely cancelling or reexecuting processing steps. The invention is simplified in both hardware and software, and can easily cope with expansion of the number of stages.

Growing community of inventors

Itami, Japan

Toru Shimizu