Kabushiki Kaisha Toshiba

Nec Corporation

Toshiba Electronic Devices & Storage Corporation

Other

Toru Sano

Hisao Kawaura

Kazuhiro Iida

Noriyuki Iguchi

Masakazu Baba

Wataru Hattori

Hiroko Someya

Toshitsugu Sakamoto

Yutaka Yamada

Kazuo Mochizuki

Katsutoshi Takahashi

Minoru Asogawa

Takashi Miyamori

Hiroyuki Ogata

Maki Sano

Yoshiko Yoshihara

Yasuki Tanabe

Sachiko Suzuki

Hui Xu

Machiko Fujita

Takashi Isogai

Shigeru Usuda

An image processing apparatus includes a calculation circuit configured to calculate a disparity between images, a determination circuit configured to determine a pixel position at which intensive disparity retrieval is to be performed based on distribution statistics of the disparity, an interpolation circuit configured to generate an interpolated image by performing interpolation at pixel positions at which intensive disparity retrieval is to be performed, and an output circuit configured to output a corrected disparity with which the distance to the object is determined. The calculation circuit calculates a first disparity based on the first and second images and generate distribution statistics from the first disparity in the first image, and calculates a second disparity based on the second image and the interpolated image generated from the first image by the interpolation circuit. The output circuit generates the corrected disparity based on differences between the first and second disparities.

Image processing apparatus, image processing program, and driving assistance system

An image processing apparatus according to an embodiment includes a disparity-specific cost value calculation circuit configured to calculate the cost value of a disparity calculation target pixel in a source image and the cost value of cost value calculation target pixels at respective positions, in the horizontal direction, of pixels arranged from a position of the disparity calculation target pixel in a reference image up to a position by a maximum disparity apart from the disparity calculation target pixel at respective positions in the horizontal direction, an inter-line minimum cost value extraction circuit configured to extract a minimum cost value from a plurality of pixels which have the same positions in the horizontal direction as the positions of the cost value calculation target pixels, and a cost optimization operation circuit configured to perform a cost optimization operation through global optimization using the cost value corresponding to one line.

Image processing apparatus and image processing system

An operation device according to an embodiment includes an operation instruction circuit, an operation circuit, a buffer and a storage area instruction circuit. The operation instruction circuit issues an operation instruction for an operation type of either one of a first operation and a second operation. The operation circuit performs an operation in accordance with the operation instruction, and outputs an intermediate operation result. The buffer stores the intermediate operation result. The storage area instruction circuit specifies an area within the buffer in Which the intermediate operation result is stored, according to the operation type.

Operation device and operation system

According to one embodiment, an image processing apparatus is provided with a first arithmetic unit, a second arithmetic unit, a third arithmetic unit, and a search unit. The first arithmetic unit calculates a first cost function. The first cost function represents a relation between a disparity value and a cost in a search range of a second image. The second arithmetic unit calculates a second cost function. The second cost function is a sum of first cost functions regarding a plurality of paths. The third arithmetic unit calculates a representative value of intermediate data. The intermediate data is an addition result of first cost functions regarding a first path group among the plurality of paths.

Image processing apparatus and image processing method

An image processing apparatus includes: a first cost calculating section configured to calculate similarity degrees between a first pixel in a first image and plural second pixels located in a horizontal-direction first range in a second image, and extract a second pixel with a highest similarity degree; a second cost calculating section configured to calculate a similarity degree between plural third pixels in a vertical-direction second range including the extracted second pixel and the first pixel and extract a third pixel with a highest similarity degree; an amount-of-difference buffer recording difference between a vertical-position of the extracted third pixel and the first pixel as an amount of difference; and a second position setting section configured to determine positions of the second pixels for which a similarity degree to the first pixel for which a disparity is calculated next is calculated.

Image processing apparatus, image processing system, and image processing method

When making a diagnosis by synthetically taking into account the information obtained by preparing a plurality of samples using different staining methods or the like and sequentially observing the samples, a diagnostician must remember information about the plurality of samples. The present invention includes image storage means for storing a reference image obtained by photographing a predetermined stained sample of and a comparison image obtained by photographing another stained sample of substantially identical biological tissues, partial image creation means for detecting a structure of the biological tissue from the reference image, cutting out from the comparison image a partial image that contains the structure detected, and storing into partial image storage means the partial image in association with the structure and the comparison image, image output means for outputting a result image that includes the reference image and the partial image, and the partial image storage means.

Diagnosis assisting system, diagnosis assisting method, and program thereof

An image recognition apparatus in an embodiment includes a feature-value calculating section configured to calculate a feature value in a region of interest segmented from an image, a likelihood calculating section configured to calculate likelihood of an object present in the region of interest referencing the feature value including a plurality of feature value elements and dictionary data including a plurality of dictionary elements, and a dictionary control section configured to acquire the dictionary element corresponding to the feature value element exceeding a set value.

Image recognition apparatus, image recognition system, and image recognition method

In an embodiment, a division circuit has an overflow determination circuit configured to determine whether or not a division result overflows by comparing absolute values of a dividend and a divisor, a replacement circuit configured to replace the dividend with a first value and replace the divisor with a second value when the overflow determination circuit determines that the division result overflows, and a stepwise division circuit configured to perform stepwise division on the dividend and the divisor or the first value and the second value.

Division circuit and microprocessor

According to an embodiment, a cache memory control circuit includes: a hit determination section; a refill processing section; a search section configured to determine a refill candidate way by searching for the way candidate for a refill process from a plurality of ways based on an LRU algorithm when the hit determination section detects a cache miss; a binary tree information section configured to store binary tree information for the LRU algorithm; a conflict detection section; and a control section. The control section updates the binary tree information in the binary tree information section by using way information of the way where the refill process is being executed when the conflict detection section determines that the way where the refill process is being executed and the refill candidate way match each other.

Cache memory control circuit and processor

A processing unit of the embodiments includes an instruction memory that holds a plurality of instructions specified by addresses, and that cannot execute read and write operations concurrently, an error correction circuit that detects and corrects an error in the instruction, a program counter, an instruction buffer that holds the instruction corrected as a corrected instruction, a program counter buffer that holds an address of the instruction where an error has been detected, a selector that selects and outputs any of the output of the error correction circuit and the output of the instruction buffer, and a control unit that controls the read and write of the instruction specified by the address from and into the instruction memory. The control unit writes the corrected instruction in the instruction memory using an address held in the program counter buffer when a predetermined condition is satisfied after the occurrence of the error.

Processing unit and error processing method

A table for changing destination has a destination address in a shared memory and an identifier of a router directly connected to a destination core, in association with each other, and is set by a source core. A search unit performs a first search for searching whether the table has an effective entry having the same address as the destination address in the shared memory, and stored in a header of a write request packet received by the source core. A route calculation unit performs a route calculation with a destination that is a router of an identifier of the entry, if the effective entry is found as a result of the first search. A header generator stores the router identifier obtained by the route calculation in a hop router field of the header of the write request packet, and sets a rerouted flag representing a change in destination.

On-chip router and multi-core system using the same

A channel () formed in a substrate () branches into channels () at a branch point (). On this branch point, obstacles () having a columnar structure are aligned at certain intervals.

Particle manipulation unit, chip and detection device having the same, mounted thereon, and methods of separating, capturing and detecting proteins

A microchipis employed as target board of mass spectrometry. The microchipincludes a substrate, a plurality of sample-distributing sections, provided in the substrateand contains samples that serve as a target of a mass spectrometry distributed therein, and a reference material-supplying channel provided in the substrateand capable of being supplied with a reference material in the mass spectrometry. The plurality of sample-distributing sections are provided in the lateral side of the fine channelfor distributing the reference material along the fine channelfor distributing the reference material.

Microchip, method for using such microchip and mass spectrometry system

A channel formed on a chip is opened without contaminating contents of the channel. Channels () and () provided on a substrate () are covered by pressing a lid () composed of a resin layer () and a plate-like lid () to a surface of the substrate (). A fixing device has a retainer plate (), which retains the plate-like lid () of a chip (), a board () on which the substrate () is placed, and a screw (). When covering the channels () and (), the screw () is fastened and the lid () is pressed to the substrate () to be fixed. And, when opening an upper portion of the channels () and (), the screw () is turned upward and a pressure is released, and the lid () is removed from the upper potion of the substrate ().

Chip, device using the chip, and method of using the same

After a sample is previously separated into plural components in a channel formed in a microchip (), the channel is irradiated along a separation direction with a laser beam from a laser oscillator () to sequentially ionize each fraction separated in the channel. The ionized fraction is detected by a mass spectrometry unit () and analyzed by an analytical result analyzing unit (). The analytical result is stored in a memory () while associated with position information in a driver control unit () and information on laser beam irradiation condition in a laser control unit (), and the analytical result is imaged by an imaging unit (). The imaged analytical result is displayed on a display ().

Growing community of inventors

Kawasaki Kanagawa, Japan

Toru Sano