Fujitsu Corporation

Toru Osajima

Kenji Suzuki

Shigenori Ichinose

Koji Banno

Shogo Tajima

Yoshio Kajii

Shigenobu Satoh

Hiroyuki Yamamoto

Hiroshi Miyazaki

Noboru Yokota

Takashi Yoneda

Takanori Nawa

Takashi Iida

Toshiaki Sugioka

Kouji Tsunetou

Masuo Inui

Masashi Takase

Sachi Kuroda

Koji Tsuneto

Modulestoare disposed in a chip, and the moduleincludes a plurality of external buffer cellsdisposed along the peripheral of the module, and an internal circuitdisposed inside the plurality of external buffer cells. Input and output of signals is made between the internal circuitand the external circuit, through the external buffer cells. The output-stage transistor of each external buffer cell has a larger size than the transistor size of the internal circuit. The external buffer cellshave a driving capability for enabling direct driving of a transistor inside the chip through a wire having the maximum Manhattan length of a module-disposed region in on chip. If the disposed area of the plurality of external buffer cellsis not sufficient, the size of the module is enlarged, or repartition is made to reform the modules so that the plurality of external buffer cellshave their sufficient disposed area.

Integrated logic circuit and hierarchical design method thereof

A semiconductor integrated circuit includes pads, a first power supply I/O cell which is connected to an external pin through a corresponding one of the pads, and a second power supply I/O cell which is not connected to an external pin through a corresponding one of the pads, but receives power supply from the first power supply I/O cell.

Semiconductor integrated circuit configured to supply sufficient internal current

A base cell is configured such that P-type regionstoare arrayed in a column direction in an N-type well, N-type regionstoare arrayed in a column direction in a P-type wellnext to the N-type well, gate linesA andB passing above a channel between the P-type regions and further between the N-type regions are formed in a row direction, and well contact regionsC andC are formed in the wellsandat outer ends thereof, respectively, while no gate contacts are formed at the outer ends. Power supply lines VDD and VSS connected to the well contact regions are formed in the column direction in a second wiring layer above a first wiring layer.

Semiconductor integrated circuit having high-density base cell array

A method of determining wire layouts of a circuit in a semiconductor device that includes a plurality of modules each corresponding to a circuit block includes the steps of providing module terminals of modules to be connected together in a same single layer, determining layouts of wires connected to the module terminals inside the respective modules by laying out the wires in one or more layers no higher than the single layer, and determining layouts of inter-module wires connecting between the module terminals by laying out the inter-module wires in the one or more layers no higher than the single layer.

Method and system for designing wire layout without causing antenna error

In a higher layer, power source wiring is provisionally provided between a logic-decided functional block and the logic-undecided functional block. Then, a resistor network of the power source wiring within the logic-undecided functional block is prepared by assuming that a current source has been connected to a power source terminal of the logic-undecided functional block. A resistor network of a total power source wiring in the higher layer is prepared by using this local resistor network. An optimum width of the power source wiring is determined by analyzing this resistor network. Based on the width, the power source wiring of the higher layer is rewired.

Method of designing wiring for power sources in a semiconductor chip, and a computer product

A base cell is configured such that P-type regions to are arrayed in a column direction in an N-type well , N-type regions to are arrayed in a column direction in a P-type well next to the N-type well, gate lines A and B passing above a channel between the P-type regions and further between the N-type regions are formed in a row direction, and well contact regions C and C are formed in the wells and at outer ends thereof, respectively, while no gate contacts are formed at the outer ends. Power supply lines VDD and VSS connected to the well contact regions are formed in the column direction in a second wiring layer above a first wiring layer.

A semiconductor integrated circuit device in which connections within and between logic unit cells can be efficiently made is provided. Logic unit cells each including a plurality of basic cells are extended in an X-direction. To form one logic unit cell, second-layer wiring regions for making connections within the logic unit cell are formed in the X-direction, i.e., the extending direction. If there are five Y-coordinate channels, the second-layer wiring regions are formed only at one Y-coordinate channel. Second-layer wiring regions for connecting logic unit cells are also formed in the X-direction, and can be situated at any of the remaining four Y-coordinate channels.

Semiconductor integrated circuit device and method of producing the same

A design support apparatus for semiconductor devices that is used to quickly arrange a non-logic cell for reducing electromagnetic radiation from a semiconductor device at the time of designing it. In this design support apparatus for semiconductor devices, a layout section does a layout for logic cells and wiring patterns to connect the logic cells. An arranged site detecting section detects an arranged site, being a site which contains neither the logic cells nor a prohibited area, after a layout is done by the layout section. A non-logic cell pattern store section stores non-logic cell patterns. A prohibited area containing site detecting section detects a prohibited area containing site, being a site which only contains a prohibited area. A non-logic cell arranging section arranges non-logic cells on the arranged site. Furthermore, the non-logic cell arranging section compares the arrangement of the prohibited area on the prohibited area containing site with a non-logic cell pattern and arranges non-logic cells only on a site where these do not conflict with each other.

Design support apparatus for semiconductor devices

A semiconductor device includes multi-pin I/O buffers. The I/O buffers are located near an I/O pad area of the device. The multi-pin I/O buffers include multiple, generally L-shaped terminals that are connected to pads in the I/O pad area with wirings. The terminals of the I/O buffers include a horizontal terminal section and a vertical terminal section. The horizontal terminal sections extend in a width direction from a corner of the buffer toward a middle point of a side of the buffer, and the vertical terminal section extends in a length direction from the corner of the terminal toward a middle point of a side of the buffer. The wirings may also be generally L-shaped.

Layout method of a semiconductor device

A semiconductor integrated circuit includes a semiconductor chip; an inner cell region; a plurality of input/output cell regions which are located around the inner cell region, and a plurality of pads which are provided between the plurality of input/output regions and sides of the semiconductor chip. Each unit area of the plurality of input/output cell regions is assigned to a corresponding input/output cell so as to be just sufficient for the corresponding input/output cell.

Growing community of inventors

Kawasaki, Japan

Toru Osajima