Fujitsu Corporation

Toru Okabayashi

Koutarou Tagawa

Yasushi Nagano

An offset address generator generates a plurality of offset addresses at an interval of a basic processing unit size on the basis of an access destination address from a calculating circuit, partitions an access destination memory region from the calculating circuit to set a plurality of verification address ranges. A determiner sequentially determines whether the plurality of set verification address ranges are matched with a monitoring target address. With this configuration, it is possible to simplify the configuration of a debug function in a processor.

Calculation processing apparatus, and method for controlling calculation processing apparatus

The invention is the microcontroller, which comprises CPU, a bus controller, an instruction address bus of a first bit number and an instruction code bus of a second bit number, which connect between the CPU and bus controller, and, further, a debug support unit, which is connected to the instruction address bus and instruction code bus. This debug support unit is also connected to an external in-circuit emulator via a tool bus of a third bit number that is smaller than the first bit number and via a bus-status signal line that reports on the status of this tool bus. The debug support unit has a data output circuit, which, in response to the status information signal, when the branch information contains a branch, outputs the converted instruction address serially to the tool bus, and when the branch information contains no branch, outputs a branchless signal to the tool bus.

Microcontroller with debug support unit

A processing unit has an operation unit and a cache memory, and further has a debug support unit and a non-cache control circuit. The debug support unit outputs a debug mode signal when an address of a program being currently executed and an optional address set for debugging coincide with each other, and the non-cache control circuit controls the operation of the cache memory via the debug mode signal and outputs the debug mode signal externally of the processing unit.

Growing community of inventors

Kawasaki, Japan

Toru Okabayashi