Toyoda Gosei Co., Ltd.

Toru Oka

Nariaki Tanaka

Yukihisa Ueno

Kazuya Hasegawa

Noriaki Murakami

Takahiro Sonoyama

Junya Nishii

Kota Yasunishi

Takaki Niwa

Tsutomu Ina

Kiyotaka Mizukami

The present invention provides a semiconductor device in which the contact resistance of the body electrode is reduced without reducing the channel mobility. The p-type layer is a Mg-doped p-GaN layer deposited on the first re-type layer. The p-type layer has a two-layer structure in which a first p-type layer and a second p-type layer are sequentially deposited. The second p-type layer has a Mg concentration higher than the Mg concentration of the first p-type layer. The recess is formed in a predetermined position on the surface of the second n-type layer, and has a depth passing through the second n-type layer and reaching the second p-type layer. The body electrode is formed on the bottom surface of the recess in contact with the p-type layer exposed thereon.

Semiconductor device

To provide a semiconductor device including an electrode having a low contact resistance with the back surface of a GaN substrate and being suitably bonded with solder, and having a low electric resistance of the current flowing in a vertical direction. The semiconductor device has a GaN substrate, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a body electrode, a drain electrode, a source electrode, and a gate electrode. The drain electrode has a Ti layer, an Al layer, a Ti layer, a TiN layer, a Ti layer, a Ni layer, and an Ag layer sequentially from the second surface of the GaN substrate.

The likelihood of formation of a corner resulting from a recess in a part of an n-type semiconductor layer is reduced at a deeper position than a p-type semiconductor layer. A method of manufacturing a semiconductor device comprises: forming a gallium nitride (GaN) based n-type semiconductor layer containing n-type impurities; forming a groove by forming a first mask on a part of a surface of the n-type semiconductor layer and then etching a part uncovered by the first mask; removing the first mask; forming a gallium nitride (GaN) based p-type semiconductor layer containing p-type impurities on the surface of the n-type semiconductor layer including the groove; etching the p-type semiconductor layer so as to expose the n-type semiconductor layer at least in a range differing from a range in the presence of the groove; and forming a metal electrode contacting the exposed n-type semiconductor layer and the p-type semiconductor layer.

Method of manufacturing semiconductor device

To restrain a side portion of a trench from being damaged by ion implantation. A method for manufacturing a semiconductor device comprises a stacking process, an ion implantation process, a heat treatment process, a groove forming process, and a first electrode forming process. In the stacking process, a p-type semiconductor layer is stacked on a first n-type semiconductor layer. In the ion implantation process, an n-type impurity or a p-type impurity is ion-implanted into a position on a surface of the p-type semiconductor layer. The position is away from a position where a groove is to be formed. In the heat treatment process, heat treatment is performed to activate the ion-implanted impurity so as to form an implanted region and to diffuse a p-type impurity in the p-type semiconductor layer into the first n-type semiconductor layer located below the implanted region so as to form a p-type impurity diffused region. In the groove forming process, the groove that penetrates the p-type semiconductor layer and has a bottom portion located in the first n-type semiconductor layer is formed. In the first electrode forming process, the first electrode is formed on an insulation film on a surface of the groove.

Semiconductor device and method for manufacturing the same

An n-type GaN layer, a p-type diffusion region formed by ion implantation and annealing in a part of the n-type layer, and a Schottky electrode are formed on the n-type layer. A region without the p-type region is defined as region A, and a region with the p-type region is defined as region B. In region A, an average density of each electron trap level of the n-type layer in a region having a depth of 0.8 &#x3bc;m to 1.6 &#x3bc;m on the n-type layer side is set so as to satisfy the predetermined conditions. In region B, an average density of each carrier trap level of the n-type layer in a region having a depth of 0.8 &#x3bc;m to 1.6 &#x3bc;m on the n-type layer side from a boundary between the n-type layer and the p-type diffusion region is set so as to satisfy the predetermined conditions.

To suppress breakage of a diode. A semiconductor device comprises a stacked body and a first electrode. The stacked body includes a first nitride semiconductor layer, a second nitride semiconductor layer, a third nitride semiconductor layer, and a fourth nitride semiconductor layer that are stacked in sequence. The first electrode is in contact with a surface of the first nitride semiconductor layer that is opposite to a surface in contact with the second nitride semiconductor layer. The semiconductor device includes a transistor forming region and a diode forming region adjacent to the transistor forming region. The transistor forming region includes a first groove, a second electrode, and a third electrode. The first groove has a bottom portion located in the second nitride semiconductor layer. The second electrode is formed on a surface of the first groove. The third electrode is in contact with a surface of the fourth nitride semiconductor layer that is opposite to a surface in contact with the third nitride semiconductor layer. The diode forming region includes a second groove and a Schottky electrode. The second groove has a bottom portion located in the third nitride semiconductor layer. The Schottky electrode makes a Schottky barrier junction with the third nitride semiconductor layer and is electrically connected to the third electrode.

A semiconductor device comprises: a gate insulating filmstacked on a semiconductor layer; and a gate electrode layerstacked on the gate insulating filmand provided to apply a voltage via the gate insulating filmfor formation of a channel in the semiconductor layer. The gate insulating filmincludes: a first insulation filmstacked on the semiconductor layer; and a second insulation filmbetween the first insulation filmand the gate electrode layer. When &#x3b5;and &#x3b5;respectively represent relative permittivities of the first and second insulation film, d[nm] and d[nm] represent film thicknesses of the first and second insulation film, and Vmax [V] represents a rated voltage applicable to the gate electrode layer, the semiconductor device is configured to satisfy &#x3b5;and meet (C1): 

An object is to use an electrode made of a less expensive material than gold (Au). A semiconductor device comprises: a first titanium layer that is formed to cover at least part of a semiconductor layer and is made of titanium; an aluminum layer that is formed on the first titanium layer on opposite side of the semiconductor layer and mainly consists of aluminum; a titanium nitride layer that is formed on the aluminum layer on opposite side of the first titanium layer and is made of titanium nitride; and an electrode layer that is formed on the titanium nitride layer on opposite side of the aluminum layer and is made of copper.

Semiconductor device and manufacturing method thereof

A semiconductor device comprises: a gate insulating filmstacked on a semiconductor layer; and a gate electrode layerstacked on the gate insulating filmand provided to apply a voltage via the gate insulating filmfor formation of a channel in the semiconductor layer. The gate insulating filmincludes: a first insulation filmstacked on the semiconductor layer; and a second insulation filmbetween the first insulation filmand the gate electrode layer. When &#x2208;and &#x2208;respectively represent relative permittivities of the first and second insulation film, d[nm] and d[nm] represent film thicknesses of the first and second insulation film, and Vmax [V] represents a rated voltage applicable to the gate electrode layer, the semiconductor device is configured to satisfy &#x2208;and meet (C1): 

A semiconductor device includes: a p-type semiconductor layer; an n-type semiconductor layer connected with the p-type semiconductor layer; a first electrode layer formed on the n-type semiconductor layer; and a second electrode layer formed on the p-type semiconductor layer. The first electrode layer and the second electrode layer are electrically connected such as to each operate at an identical potential. The second electrode layer is connected with at least a part of a surface of the first electrode layer which is opposite to a surface of the first electrode layer that is in contact with the n-type semiconductor layer.

An object is to use an electrode made of a less expensive material than gold (Au). A semiconductor device comprises: a first titanium layer that is formed to cover at least part of a semiconductor layer and is made of titanium; an aluminum layer that is formed on the first titanium layer on opposite side of the semiconductor layer and mainly consists of aluminum; a titanium nitride layer that is formed on the aluminum layer on opposite side of the first titanium layer and is made of titanium nitride; and an electrode layer that is formed on the titanium nitride layer on opposite side of the aluminum layer and is made of silver.

A semiconductor device includes: a p-type semiconductor layer; an n-type semiconductor layer; a first electrode layer; a second electrode layer; and a control electrode layer. The first and second electrode layers are electrically connected such as to each operate at an identical potential. The first electrode layer is connected with a part of a surface of the second electrode layer which is opposite to a surface of the second electrode layer that is in contact with the p-type semiconductor layer. The second electrode layer is connected with a connection line which is a part of a peripheral line of a joint interface between the p-type semiconductor layer and the n-type semiconductor layer on an interface side between the second electrode layer and the p-type semiconductor layer, and is formed to be extended to a position on a control electrode layer side of the connection line.

Semiconductor Device

A device comprises a substrate, an n-layer and a p-layer, an n-electrode, and a p-electrode. A step is formed at an outer circumference of the device. A protective film is formed so as to continuously cover a side surface and a bottom surface of the step. A field plate electrode connected with the p-electrode is formed on the protective film. When a distance from the pn junction interface to the surface of the protective film on the bottom surface of the step is defined as h (&#x3bc;m), a dielectric constant of the protective film is defined as &#x2208;, and a thickness of the protective film at the pn junction interface on the side surface of the step is defined as d (&#x3bc;m), (&#x2208;&#xb7;h)/d is 4 or more, and &#x2208;/d is 3 (1/&#x3bc;m) or more.

A semiconductor device includes; a semiconductor layer mainly made of GaN; a protective film provided to have electrical insulation property and configured to coat the semiconductor layer; and an electrode provided to have electrical conductivity and configured to form a Schottky junction with the semiconductor layer. The protective film includes: a first layer made of AlOand arranged adjacent to the semiconductor layer; a second layer made of an electrical insulation material different from AlOand formed on the first layer; and an opening structure formed to pass through the first layer and the second layer. The electrode is located inside of the opening structure.

A semiconductor device includes a first n-type semiconductor layer, a p-type semiconductor layer, a second n-type semiconductor layer and a trench. The first n-type semiconductor layer includes a first interface and a second interface. The second interface forms an upper surface of a convex protruded from the first interface. The p-type semiconductor layer is stacked on the first n-type semiconductor layer and includes a first region stacked on the first interface and a second region stacked on the second interface. The first region is uniformly continuous with the second region. The second n-type semiconductor layer is stacked on the p-type semiconductor layer. The trench is depressed from the second n-type semiconductor layer through the p-type semiconductor layer into the convex of the first n-type semiconductor layer.

Semiconductor device including first interface and second interface as an upper surface of a convex protruded from first interface and manufacturing device thereof

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Kiyosu, Japan

Toru Oka