Hitachi, Ltd.

Toru Ohtsuki

Yoshio Oshima

Sako Ishikawa

Masaharu Fukuta

Hidenori Umeno

Taro Inoue

Shunji Tanaka

Hideaki Yabe

Tadashi Yamamoto

Hideo Sawamoto

Kiyoshi Ogawa

Ryo Yamagata

Masaya Watanabe

Masatoshi Haraguchi

Toshiaki Kawamura

Hiroaki Sato

Hiroo Miyadera

A plural-OS run system in which a plurality of operating systems (OSs) capable of operating on machines of different architectures, respectively, are allowed to run on one bare machine under the control of one control program (CP) or one control means. The input/output instruction and input/output interrupt of the operating system capable of running on a machine of the same architecture as that of the bare machine are directly executed on the bare machine without need for translation of the format. The input/output instruction and the input/output interrupt of the operating system adapted to run on a machine of the architecture differing from that of the bare machine are allowed to be directly executed while translating the format.

Input/output execution apparatus for a plural-OS run system

A system and method for continuous operation of a virtual machine system having operation modes including a guest mode in which virtual machines are operated and a nonguest mode in which a virtual machine monitor for controlling the virtual machines is operated. The continuous guest is a virtual machine which does not stop executing operation at the occurrence of a failure due to program error of the virtual machine monitor. A main storage is provided with two areas. One of the two areas is a continuous guest area having the same host absolute address in the nonguest mode as a guest absolute address in the guest mode, the area is used by the continuous guest which is a virtual machine which continues to operate on transition of the operation mode from the guest mode to the nonguest mode. The other is an area in which a program module for dispatching the continuous guest in response to the transition of the operation mode from the guest mode to the nonguest mode. The continuous guest is allocated to the guest area on transition of the operation mode from the guest mode to the nonguest mode. Occurrence of a failure due to a program error of the virtual machine monitor is detected and by starting the program module for dispatching the continuous guest in response to the detection of the occurrence of the failure, the operation of the continuous guest does not stop executing.

System for recovery from a virtual machine monitor failure with a

In a virtual machine system in which a virtual machine directly executes operations by use of the hardware without an intervention from the virtual machine control program (VMCP), at an occurrence of an input/output interruption, the system sets to a storage an event that the input/output interruption has been accepted and reserved by the VMCP. When the virtual machine processes interruption information by means of the hardware without an intervention of the VMCP, the virtual machine resets the state of the storage. When the virtual machine is set to an interruptible state, control is passed to the VMCP. The VMCP tests to determine whether or not the virtual machine has reset the state of the storage, thereby judging an acceptability of the interruption.

Virtual machine system with vitual machine resetting store indicating

A virtual machine system which includes a plurality of virtual machines by using a computer system of a multi-processor configuration having a plurality of real instruction processors and a real main storage which is divided into a plurality of storage regions to be allocated to the virtual machines, respectively. Each of the virtual machines is so organized as not to make access to the regions allocated to the other virtual machines. When one and the same virtual machine includes a plurality of real instruction processors, invalidation of entry of a buffer storage of another real instruction processor as conditioned by execution of a predetermined instruction by a real instruction processor is performed only for the other real instruction processor assigned to the same virtual machine as the real instruction processor and is inhibited from affecting the real instruction processors assigned to the other virtual machines.

Virtual machine system having a plurality of real instruction processors

A virtual machine system for executing fast speed address translation in plural virtual machines having a two-stage address translation mechanism. The system permits address translation to be executed by adding to an output from a first address translation address constants in a hold apparatus holding address constants including zero, executing a second address translation, and selecting an output from the first address translation to which the address constants have been added or an output from the second address translation. An address translation for a plurality of different regions is performed by switching a value for the address constants held by the hold apparatus.

Virtual machine system which translates virtual address from a selected

An address space switching apparatus has a group of conventional registers capable of storing address information and a group of additional registers capable of storing address information longer than the address information stored by the group of conventional registers. The register length of the group of additional registers is not restricted by the length of the group of conventional registers and is selected to be of a magnitude sufficient to define a desired operand address space. Information items stored in the group of additional registers such as a base address and an index value associated with the extended address space are selected when an operand address is to be generated so as to be appropriately employed for the address computation, thereby supplying address information having a length sufficient for the extended address space. On the other hand, when an address other than an operand address is to be created, information items stored in the group of conventional registers are selected so as to be utilized in the address computation.

Address space switching apparatus

An apparatus for decimal multiplication divides a multiplier of binary coded decimal (BCD) into plural groups, generates plural partial products of which are multiplied a multiplicand of BCD and the plural groups of multiplier over successive cycles and adds them to an intermediate product which is a summation of the previously generated partial products. The addition of the partial product and the intermediate product is made by a carry save adder. At a first cycle, the intermediate product is set to zero, and the addition of 6 is made to each digit of either one of the intermediate product sum and the partial product, and the addition of the partial product and the intermediate product is made by a carry save adder loop over successive cycles. At a final cycle, the sum and carry from the carry save adder are added by a full adder, and the subtraction of 6 is made for each digit according to the existence of carry transfer in each digit of the full adder and the resultant value is output as a multiplication result.

Apparatus for decimal multiplication

A binary coded decimal number division apparatus in which a quotient represented in a binary coded decimal notation is determined on digit-by-digit basis by using a quotient prediction table and a group of multiple value registers and in which a predicted quotient read out from the quotient prediction table is used intact when the predicted quotient is correct while otherwise the predicted quotient is decremented by one, wherein the values stored in the quotient prediction table together with redundant bit are previously modified to (0110).sub.2 to (1111).sub.2 in the binary coded decimal representation. The multiple value register is selected by using three of the four bits of the modified predicted quotient, while upon determination of the quotient, the value used for modification is subtracted from the output value of the quotient prediction table to thereby derive the predicted quotient of one digit. With this arrangement, three of the four bits of the predicted quotient of one digit read out from the quotient prediction table can be used directly as the selection signal for selecting the relevant divisor multiple register.

Binary coded decimal number division apparatus

In preparation of addresses of a quotient prediction table used in a binary coded decimal number division scheme with predetermined bits of a dividend and a divisor in binary coded decimal representation, the addresses are modified with the redundant bits. The absolute bit number for the addresses is thus decreased, whereby data quantity and hence capacity of RAM required for implementing the quotient prediction table can be significantly reduced, while satisfactory function of the quotient prediction table being assured. The apparatus for the binary coded decimal number division is implemented inexpensively in a small size.

A multiplier device comprising hold means for holding the result of addition, block product means for producing k block products each having 2n bits, where n is an integer equal to or greater than 2, the k block products being formed by multiplying each block by n bits, k blocks being obtained by dividing a multiplicand at intervals of n bits from the least significant bit of the multiplicand, and adder means for adding two groups of block products to the output of the hold means, the two groups of block products consisting of alternate block products out of the k block products from the block product means.

Growing community of inventors

Hadano, Japan

Toru Ohtsuki