Hitachi, Ltd.

Other

Equator Technologies, Inc.

Renesas Electronics Corporation

Renesas Technology Corp.

Toru Nojiri

John Setel O'Donnell

Benjamin Franklin Cutler

Yatin Mundkur

Woobin Lee

Christopher H Basoglu

Gregorio Gervasio

David Baker

Keiji Kojima

Kiyokazu Nishioka

Takeshi Miyazaki

Radhika Thekkath

Eric Carl Rehm

Richard Deeley

Atsuo Kawaguchi

Ashok Raman

Vinay Naik

Sarang Padalkar

Yasunori Kaneda

Yoshiki Kurokawa

Koichi Terada

Kazuhiko Tanaka

Yoshifumi Fujikawa

Koji Hosoki

Masayasu Asano

Takashi Matsumoto

Yuki Kondoh

Keisuke Toyama

Harushi Someya

David R Poole

Takehiko Nagano

Tomohiko Shigeoka

John Poole, Legal Representative

A data processor includes: a central processing unit (CPU), in which a plurality of virtual machines (), each running an application program under controls of different operating systems, and a virtual machine manager () for controlling the plurality of virtual machines are selectively arranged according to information set in mode registers (); and a resource access management module () for managing access to hardware resource available for the plurality of virtual machines. The resource access management module accepts, as inputs, the information set in the mode registers and access control information of the central processing unit to the hardware resource, compares the information thus input with information set in a control register, and controls whether or not to permit access to the hardware resource in response to the access control information. As a result, redesign involved in changes in system specifications can be reduced, and a malfunction owing to resource contention can be prevented. The invention contributes to increase of security.

Data processor with virtual machine management

A CPU forced stop signal is used as means for stopping execution of a program executed on a ROM by a CPU of a target system. A time required for stopping the CPU from the issuance of the CPU forced stop signal between an ICE device and the CPU is considered and set, and a CPU forced stop signal issuance position which is prior to a stop target position is determined. Based on a real-time tracing function of the CPU, at an issuance position and timing of the CPU forced stop signal on the execution of the program, the CPU forced stop signal is issued, the CPU is stopped, and the event is acquired. By this means, an arbitrary number of events of the program can be acquired regardless of the number of breakpoint registers.

Program failure analysis system, failure analysis method, and emulator device

In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus. An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices. The internal memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules coupled to the internal memory bus. A transceiver system is coupled to the processor memory bus and the internal memory bus for transferring data between the processor memory bus and the internal memory bus.

Data streamer

An integrated multimedia system having a multimedia processor is disposed in an integrated circuit having a first host processor system coupled to the multimedia processor and a second local processor disposed within the multimedia processor for controlling the operation of the multimedia processor. A data transfer switch is coupled to the second processor for transferring data to various modules of the processor, at least one of which is a data cache. The data transfer switch transfers data in either direction between the cache and a module within the processor. A data streamer schedules simultaneous data transfers among the various-modules disposed within the multimedia processor in accordance with corresponding channel allocations. An interface unit is coupled to the data streamer and has a plurality of input/output (I/O) device driver units. A plurality of external I/O devices are coupled to the plurality of I/O device driver units via a multiplexer.

Integrated multimedia system

According to prior art techniques, it is not possible to set virtual groups of network devices between SANs and IP networks and to provide virtual connection control of network devices between SANs and IP networks. A network system having an IP network for interconnecting network devices constituting SANs, is provided with a virtual group conversion device for converting, when information including an identifier for identifying a virtual group in the IP network is received, the received identifier into an identifier for identifying a virtual group in the SANs and transmitting the converted identifier to a SAN virtual group setting device, and for converting, when information including an identifier for identifying a virtual group in the SANs is received, the received identifier into an identifier for identifying a virtual group in the IP network and transmitting the converted identifier to an IP virtual group setting device.

Connection control device, method and program

An integrated multimedia system has a multimedia processor disposed in an integrated circuit. A processor is disposed within the multimedia processor which controls the operation of the multimedia processor. A data transfer switch is disposed within the multimedia processor and coupled to the processor which transfers data to various modules of the multimedia processor. A fixed function unit is disposed within the multimedia processor, coupled to the processor and the data transfer switch. A data streamer is coupled to the data transfer switch, and configured to schedule simultaneous data transfers among a plurality of modules disposed within the multimedia processor in accordance with the corresponding channel allocations. As interface unit is coupled to the data streamer and has a plurality of I/O device driver units. A multiplexer coupled to the interface unit provides access between a selected number of I/O device driver units and external I/O devices via output pins.

A computer system includes a plurality of computers and at least one storage connected to the plurality of computers. The storage includes a device that obtains information concerning areas within the storage that are used by the respective plurality of computers, a device that obtains information concerning a capacity within each of the areas that is used by each of the plurality of computers to store-data, and a device that notifies at least one of the plurality of computers of a status of the areas within the at least one storage. The computer system utilizes and manage the storage, without having each of the computers utilize and manage the storages with regard to storage capacity.

Computer system obtaining information on capacity and usage of an area used by a computer and notifying the computer the status thereof

Data transfer engine of a processor having a plurality of modules

As far as multimedia processing is concerned, a plurality of computations of a same type are often executed concurrently and hence a plurality of computing units having a same function are used and mode information for controlling the plurality of units by an instruction unit for one computing unit is prepared in each instruction to execute a plurality of computations with a single instruction.

Processor including a plurality of computing devices

An object of the prevent invention is to provide a processor that can execute many computations with a small number of instruction codes. As far as multimedia processing is concerned, a plurality of computations of a same type are often executed concurrently and hence a plurality of computing units having a same function are used and mode information for controlling the plurality of units by an instruction unit for one computing unit is prepared in each instruction to execute a plurality of computations with a single instruction.

Parallel computing units having special registers storing large bit widths

Integrated multimedia system with local processor, data transfer switch, processing modules, fixed functional unit, data streamer, interface unit and multiplexer, all integrated on multimedia processor

Growing community of inventors

Tokyo, Japan

Toru Nojiri