Matsushita Electric Industrial Co., Ltd.

Matsushita Electronics Corporation

Other

Toru Nasu

Yoshihisa Nagano

Akihiro Matsuda

Koji Arita

Eiji Fujii

Atsuo Inoue

Yasuhiro Shimada

Yasuhiro Uemoto

Tatsuo Otsuki

Taketoshi Matsuura

Keisuke Tanaka

Takumi Mikawa

Shinichiro Hayashi

Masamichi Azuma

Toshie Kutsunai

Toyoji Ito

Yasufumi Izutsu

Keisaku Nakao

Carlos Alberto Paz De Araujo

Michael C Scott

Joseph D Cuchiaro

Hajime Yasuoka

Yoshihiro Shimada

A semiconductor device comprises: an insulating film formed over a semiconductor substrate and having a first recess; a plurality of capacitor elements each of which is composed of a capacitor lower electrode formed on wall and bottom portions of the first recess and having a second recess, a capacitor insulating film of a dielectric film formed on wall and bottom portions of the second recess and having a third recess, and a capacitor upper electrode formed on wall and bottom portions of the third recess; and a conductive layer (referred hereinafter to as a low-resistance conductive layer) which is formed to cover at least portions of the respective capacitor upper electrodes constituting the plurality of capacitor elements and to extend across the plurality of capacitor elements and which has a lower resistance than the capacitor upper electrode.

Semiconductor device and method for fabricating the same

A method of making a ferroelectric thin film includes the step of forming a ferroelectric thin film with a randomly oriented layered structure on a surface of a conductor layer. At least the surface of the conductor layer has a spherical crystal structure.

Method of making ferroelectric thin film having a randomly oriented layer and spherical crystal conductor structure

The semiconductor device of the invention includes a capacitor device, which is formed on a substrate and which includes a capacitive lower electrode, a capacitive insulating film made of an insulating metal oxide film and a capacitive upper electrode. An interlevel insulating film having an opening reaching the capacitive upper electrode is formed over the capacitor device. A metal interconnection including a titanium film is formed over the interlevel insulating film so as to be electrically connected to the capacitive upper electrode through the opening. An anti-diffusion film having conductivity is formed between the capacitive upper electrode and the metal interconnection for preventing titanium atoms composing the titanium film of the metal interconnection from passing through the capacitive upper electrode and diffusing into the capacitive insulating film.

The semiconductor memory device of the present invention includes: an interlayer insulating film formed on a semiconductor substrate; a contact plug formed to extend through the interlayer insulating film; and a capacitor formed on the interlayer insulating film so that an electrode of the capacitor is connected with the contact plug. The electrode has an iridium oxide film as an oxygen barrier film. The average grain size of granular crystals constituting the iridium oxide film is a half or less of the thickness of the iridium oxide film.

Semiconductor device having a capacitor comprising an electrode with an iridium oxide film as an oxygen barrier film

The ferroelectric capacitor device includes a bottom electrode, a capacitor insulating film formed of a ferroelectric film, and a top electrode. The ferroelectric film has a bismuth layer structure including a plurality of bismuth oxide layers and a plurality of perovskite-like layers alternately put on top of each other. The plurality of bismuth oxide layers are formed of Bi O , and the plurality of perovskite-like layers include two or more kinds of layers represented by a general formula: A B O (where A is a univalent, divalent or trivalent metal, B is a tetravalent, pentavalent or hexavalent metal, m is an integer equal to or more than 1, at least one of A being Bi if m is an integer of 2 or more, and 0&lE;&agr;&lE;1) and different in the value of m.

Ferroelectric capacitor device

The ferroelectric film of the invention is made from a ferroelectric material represented by a general formula, Bi A Ti O or (Bi A Ti O ) &plus;(DBi E O ) , wherein A is an element selected from the group consisting of La, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and V; D is an element selected from the group consisting of Sr, Ba, Ca, Bi, Cd, Pb and La; E is an element selected from the group consisting of Ti, Ta, Hf, W, Nb, Zr and Cr; and 0&lE;x&lE;2, 0<y&lE;(4&minus;x)&times;0.1 and 0.5<z<1.

Ferroelectric film and semiconductor device

A contact plug is formed in a contact hole, which has been formed through a passivation film on a substrate, so that a recess is left over the contact plug. Then, the passivation film is dry-etched so that the opening of the recess is expanded or that the depth of the recess is reduced. After that, lower electrode, which will be connected to the contact plug, capacitive insulating film of an insulating metal oxide and upper electrode are formed in this order to make a capacitor.

Method for fabricating semiconductor memory device having a capacitor

A semiconductor memory device, includes: a semiconductor substrate including a transistor; a first protective insulating film for covering the semiconductor substrate; at least one data storage capacitor element formed on the first protective insulating film; a second protective insulating film for covering the first protective insulating film and the capacitor element; a hydrogen barrier layer; and an interconnection layer for electrically connecting the transistor and the capacitor element, wherein: the capacitor element includes a lower electrode formed on the first protective insulating film, a capacitor film formed on the lower electrode, and an upper electrode formed on the capacitor film, the capacitor film includes an insulating metal oxide, the second protective insulating film has a first contact hole reaching the upper electrode and a second contact hole reaching the lower electrode, and the hydrogen barrier layer is provided in the first and second contact holes, so as not to expose the upper and the lower electrodes.

Semiconductor memory device and method for manufacturing the same

A Ti/TiN adhesion/barrier layer is formed on a substrate and annealed. The anneal step is performed at a temperature within a good morphology range of 100&deg; C. above a base barrier anneal temperature that depends on the thickness of said barrier layer. The base barrier anneal temperature is about 700&deg; C. for a barrier thickness of about 1000 &angst; and about 800&deg; C. for a barrier thickness of about 3000 &angst;. The barrier layer is 800 &angst; thick or thicker. A first electrode is formed, followed by a BST dielectric layer and a second electrode. A bottom electrode structure in which a barrier layer of TiN is sandwiched between two layers of platinum is also disclosed. The process and structures also produce good results with other capacitor dielectrics, including ferroelectrics such as strontium bismuth tantalate.

Integrated circuit capacitors with barrier layer and process for making the same

A coating of liquid precursor for forming a layered superlattice material is applied to a substrate, the substrate is dried and then pretreated using RTP at 450 &deg; C. for 5 minutes. Following the RTP, the substrate is annealed in an unreactive gas at a temperature not exceeding 800&deg; C. then annealed in oxygen gas at a temperature not exceeding 800&deg; C. for one hour to form a thin film of layered superlattice material.

Method using unreactive gas anneal and low temperature pretreatment for fabricating layered superlattice materials and making electronic devices including same

A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm,or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10,atoms/cm,or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.

Semiconductor device having a capacitor exhibiting improved moisture resistance

A semiconductor memory device, includes: a semiconductor substrate including a transistor; a first protective insulating film for covering the semiconductor substrate; at least one data storage capacitor element formed on the first protective insulating film; a second protective insulating film for covering the first protective insulating film and the capacitor element; a hydrogen carrier layer; and an interconnection layer for electrically connecting the transistor and the capacitor element, wherein: the capacitor element includes a lower electrode formed on the first protective insulating film, a capacitor film formed on the lower electrode, and an upper electrode formed on the capacitor film, the capacitor film includes an insulating metal oxide, the second protective insulating film has a first contact hole reaching the upper electrode and a second contact hole reaching the lower electrode, and the hydrogen barrier layer is provided in the first and second contact holes, so as not to expose the upper and the lower electrodes.

Growing community of inventors

Kyoto, Japan

Toru Nasu