Mitsubishi Denki Kabushiki Kaisha

Adv Antest Corporation

The University of Tokyo

Nec Corporation

Thine Electronics, Inc.

Aika Design Inc.

Toru Nakura

Kimio Ueda

Kunihiro Asada

Masahiro Ishida

Masayuki Mizuno

Satoshi Miura

Tetsuya Iizuka

Koichi Nose

Satoshi Komatsu

Takashi Kusaka

Naoki Terao

Yoshimichi Murakami

Rimon Ikeno

Norihito Tohge

A power supply apparatus supplies a power supply voltage V. The power supply apparatus includes a compensation circuit in addition to a main power supply. The compensation circuit receives, via its input, as a feedback signal, a detection signal Vthat corresponds to the power supply voltage V. The compensation circuit has input/output characteristics fthat correspond to the characteristics of the main power supply and the characteristics of a target power supply to be emulated. The compensation circuit injects or otherwise draws a compensation current ithat corresponds to the detection signal Vto or otherwise from a node for generating the power supply voltage V.

Power supply apparatus

This embodiment relates to a clock data recovering apparatus capable of improving consecutive identical digits (CID) resistance. The clock data recovering apparatus includes a clock generating apparatus. The clock generating apparatus includes a signal selection unit, a phase detection unit, a phase control unit, a selection unit, a phase delay unit, a time measurement unit, and a phase selection unit. The phase delay unit includes a plurality of delay elements. The phase selection unit selectively outputs an output signal of any one of the plurality of delay elements as a feedback clock. The phase detection unit detects a phase relation between an edge signal and the feedback clock. The phase control unit outputs a control signal to control a signal selection operation by the phase selection unit such that a phase difference detected by the phase detection unit decreases, to the phase selection unit.

Clock generating apparatus and clock data recovering apparatus

A judgment unit judges the pass/fail of DUTs. A power supply circuit has changeable characteristics, and supplies a power supply signal to the DUTs. A condition setting unit performs a pilot test before a main test for the DUTs, and acquires a test condition to be used in the main test. The condition setting unit executes: (a) measuring a first device characteristic value for each of multiple pilot samples sampled from among the DUTs while emulating a power supply characteristic close to what is used in a user environment in which the DUT is actually used; (b) measuring a predetermined second device characteristic value for each of the multiple pilot sample devices while emulating a power supply characteristic close to what is used in a tester environment in which the main test is performed; and (c) determining the test condition based on the first and second device characteristic values.

Test apparatus

A signal conversion circuit, a PLL circuit, a delay control circuit and a phase control circuit for promoting miniaturization and for reducing quantization noise. TSTC does not require a low-pass filter of capacitor Cm with large layout area conventionally required for converting pulse width to voltage, which promotes miniaturization and cost reduction. TSTCgenerates analog voltage adequate for transition state at boundary where pulse signal transits, which reduces quantization noise, compared with conventional digital PLL circuits.

Signal conversion circuit, PLL circuit, delay adjustment circuit, and phase control circuit

Disclosed is a semiconductor integrated circuit including a first storage circuit and a second storage circuit that respectively store logic levels of an input to the delay circuit and an output of the delay circuit when a logic level of a clock line is changed, and a determination circuit that determines whether or not the results of the first storage circuit and the second storage circuit coincide or not. Even if a transistor or a wiring that constitutes the semiconductor integrated circuit has been degraded due to secular change or the like, a possibility of an anomaly or a failure in one of the operation circuits caused by the degradation can be predicted before the anomaly or the failure occurs.

Failure prediction circuit and method, and semiconductor integrated circuit

In a multiplexer, flip-flops for timing control are interposed between a control signal generating circuit and a four-to-one selector, and a flip-flop is interposed between a quarter divider and flip-flops provided for data input. A sum of delay times of the quarter divider and the control signal generating circuit and a setup time of the flip-flops for timing control is merely required to fall within one clock cycle, and therefore an operation speed can be high.

Fast operating multiplexer

A semiconductor device improved to suppress a leakage current of a transistor is provided. A gate electrode is disposed on a semiconductor substrate. A pair of p type source/drain layers are provided on the surface of the semiconductor substrate, on both sides of the gate electrode in the gate length direction Y. An n type gate width determining layer is provided on the surface of the semiconductor substrate to sandwich the source/drain layers in the width direction X of the gate electrode, which determines a gate width of the gate electrode. The source/drain layers and the gate width determining layer are isolated by PN junction.

Semiconductor device with reduced transistor leakage current

First to third D flip-flops, fourth to sixth D flip-flops, and a delay circuit are provided. The first to third D flip-flops frequency-divide a clock signal. The fourth to sixth D flip-flops are provided corresponding to the first to third D flip-flops for latching frequency-divided outputs from corresponding D flip-flops and outputting them in synchronization with the clock signal. Accordingly, the frequency-divided outputs from the fourth to sixth D flip-flops are synchronized with the clock signal with a delay of prescribed time. The delay circuit outputs the clock signal after a delay of the prescribed time. Thus, the output of the delay circuit and the frequency-divided outputs are synchronized without delay.

Synchronous frequency dividing circuit

According to a structure in which each transistor of an output buffer transistor group of a gate array structure is electrically isolated, each body potential is set independent Also, a diode-connected transistor is provided between power supplies. An element not used in the output buffer transistor group can be connected without short-circuiting power supply lines between independent power supply lines to form an electrostatic protection circuit that is efficient in layout.

Semiconductor integrated circuit device including electrostatic protection circuit accommodating drive by plurality of power supplies and effectively removing various types of surge

Counter circuits causing no noise at the time of operation are provided. Three stage of D-type flip-flops (FF1 to FF3) are connected in series. A delay element (11) delays a signal (S2) that is Q output of the flip-flop (FF1) by a delay time (d2) to output a delay signal (S2D), and a delay element (12) delays a signal (S3) that is Q output of the flip-flop (FF2) by a delay time (d3) to output a delay signal (S3D). Here, the relationship among the delay time (d2, d3) and a clock cycle (Tc) is set so as to satisfy the condition of {Tc&gt;d2&gt;d3}. NOR gate for three inputs (G1) receives delay signals (S2D, S3D) and a signal (S4) i.e., Q output of the flip-flop (FF3), and performs NOR operation on these signals (S2D, S3D and S4), thereby outputting a signal (S1) to D input of the flip-flop (FF1).

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Tokyo, Japan

Toru Nakura