Hitachi, Ltd.

Toru Nakamura

Katsumi Ogiue

Yoichi Tamaki

Hiromichi Enami

Satoru Isomura

Akihisa Uchida

Shinji Nakajima

Kiyoji Ikeda

Toru Koizumi

Jiro Kusuhara

Mitsugu Edagawa

Hideharu Ohtomo

Kaoru Ohgaya

A multilayer semiconductor integrated circuit having a plurality of wiring layers in which at least the lines of a lower layer are extended on wiring channel regions arranged in a grid. Dummy pedestals are formed of the same conductive layer as that forming the lines of the lower layer and are arranged in the intersecting areas of the wiring channel regions where none of the lines of the lower layer is placed. A method of manufacturing such a semiconductor integrated circuit comprises steps of preparing dummy pedestal layout data for arranging the dummy pedestals in all the intersecting areas of the wiring channel regions and line layout data for forming the lines of the lower layer on predetermined wiring channels among all the wiring channel regions, and combining the dummy pedestal layout data and the line layout data by logical sum (OR).

Semiconductor integrated circuit with dummy pedestals

A method of wiring electronic parts by a printed circuit board is provided. According to the method, electronic parts having pins arranged at intervals unmatched to a predetermined grid resolution are placed on the printed circuit board and the desired pins of the electronic parts are electrically connected by the printed circuit board. The characteristic of the method resides in that wiring pins are each provided at the same relative channel position within a unit grid portion located in the vicinity of each of the pins of the electronic parts so that the pins of the electronic parts are electrically connected to one another through the wiring pins.

Printed circuit board wiring method

Growing community of inventors

Tanashi, Japan

Toru Nakamura