Hitachi, Ltd.

Toru Motoya

Satoshi Nishikawa

Yusuke Kanno

Tadanobu Toba

Masahiro Shiraishi

Takumi Uezono

Hideo Harada

Keisuke Yamamoto

Goichi Ono

Hidehiro Toyoda

An information processing apparatus having an input device for receiving data, an operation unit for constituting a convolutional neural network for processing data, a storage area for storing data to be used by the operation unit and an output device for outputting a result of the processing. The convolutional neural network is provided with a first intermediate layer for performing a first processing including a first inner product operation and a second intermediate layer for performing a second processing including a second inner product operation, and is configured so that the bit width of first filter data for the first inner product operation and the bit width of second filter data for the second inner product operation are different from each other.

Information processing apparatus, image recognition apparatus, and parameter setting method for convolutional neural network

A verification method for an application logic provided with one or more macro logics configured to perform a predetermined operation, a macro operation control unit configured to instruct the one or more macro logics to start the operation to cause the one or more macro logics to perform the operation, and an operation data storage area configured to store data. In the application logic, static verification by property description of a formal verification language is performed for each of the one or more macro logic, the macro operation control unit, and the operation data storage area, and dynamic verification by simulation is further performed for at least one of the one or more macro logics.

Application logic, and verification method and configuration method thereof

Provided is a technology capable of reducing the number of resources necessary for logic implementation in a control device. A semiconductor LSI design device generates a combinational circuit configured with functional blocks defined by a functional block library from an application specification, allocates an operation order of each functional block in the combinational circuit under a condition for starting an operation of a functional block connected to an input pin after ending the operation, converts into a sequence circuit which uses the functional block twice or more in a time division manner, extracts the operation order at a time of execution of the sequential circuit, and determines whether the operation order allocated to the combinational circuit coincide with the extracted operation execution order.

Semiconductor LSI design device and design method

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Tokyo, Japan

Toru Motoya