Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Toru Morikawa

Nobuo Higaki

Keizo Sumida

Akira Miyoshi

Masato Suzuki

Shinya Miyaji

Shinji Ozaki

Jiro Miyake

Satoshi Ogura

Keisuke Kaneko

Hiroyuki Mizohata

A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction 'MCSST Dis decoded, the sum-product result registeroutputs its held value to the path PThe comparatorcompares the magnitude of the held value of the sum-product result registerwith the coded 32-bit integer '0x0000_00FF'. The polarity judging unitjudges whether the eighth bit of the value held by the sum-product result registeris &#x201c;ON'. The multiplexeroutputs one of the maximum value &#x201c;0x0000_00FF&#x201d; generated by the constant generatorthe zero value &#x201c;0x0000_0000&#x201d; generated by the zero generatorand the held value of the sum-product result registerto the data bus

Processor which can favorably execute a rounding process composed of positive conversion and saturated calculation processing

A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction 'MCSST D' is decoded, the sum-product result registeroutputs its held value to the path P. The comparatorcompares the magnitude of the held value of the sum-product result registerwith the coded 32-bit integer '0x0000_00FF'. The polarity judging unitjudges whether the eighth bit of the value held by the sum-product result registeris &#x201c;ON&#x201d;. The multiplexeroutputs one of the maximum value &#x201c;0x0000_00FF&#x201d; generated by the constant generator, the zero value &#x201c;0x0000_0000&#x201d; generated by the zero generator, and the held value of the sum-product result registerto the data bus

When an interruption instruction occurs in an information processing apparatus including a CPU and a coprocessor, execution of a single dedicated instruction 'GETACX Dm,Dn' performs saving of necessary data from all registers. 'Dm' is a value output from a general register groupto a first data input bus. Each of calculation units implemented in a coprocessorrecognizes a value stored therein. If a value &#x201c;Dm&#x201d; specifies one of the calculation units, the specified calculation unit outputs, to a selector, data stored in a register included in the specified calculation unit. An implemented calculation unit information output circuitstores therein the count of the calculation units implemented in the coprocessor. If a value of the first data input busis greater than the count of the calculation units, the implemented calculation unit information output circuitoutputs a value &#x201c;1&#x201d; to a flag register. Based on the fact that the value stored on the flag registeris &#x201c;1&#x201d;, a CPUrecognizes that saving of the data from the register has been completed.

Processing system having co-processor for storing data

A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction &ldquo;MCSST D,&rdquo; is decoded, the sum-product result register,outputs its held value to the path P,The comparator,compares the magnitude of the held value of the sum-product result register,with the coded 32-bit integer &ldquo;0x0000_00FF&rdquo;. The polarity judging unit,judges whether the eighth bit of the value held by the sum-product result register,is &ldquo;ON&rdquo;. The multiplexer,outputs one of the maximum value &ldquo;0x0000_00FF&rdquo; generated by the constant generator,the zero value &ldquo;0x0000_0000&rdquo; generated by the zero generator,and the held value of the sum-product result register,to the data bus

A first instruction requiring that a data word should be read out from a data memory and be stored in a certain register in a register set, and then a second instruction requiring that two operands, respectively read out from the register and another register in the register set, should be added are pipeline-processed. In a high-speed mode in which an operation clock having a higher frequency is supplied, a data cache intervened between an instruction execution circuit and the data memory is controlled to supply a data word to a WB (write back) stage of the instruction execution circuit within two cycles with respect to an input address associated with the first instruction. In order to execute the second instruction, the data word is supplied from the WB stage to an EX (operation execution) stage of the instruction execution circuit. In a low-speed mode in which an operation clock having a lower frequency is supplied, the data cache is controlled to supply a data word to an MEM (memory access) stage of the instruction execution circuit within one cycle with respect to an input address associated with the first instruction. In order to execute the second instruction, the data word is bypassed from the MEM stage to the EX stage.

Apparatus for pipelining sequential instructions in synchronism with an

A data processor comprises a processing unit which processes an instruction in pipeline stages, the number of which is switchable between n and m, m being a larger number than n. The data processor also comprises a switching unit for switching the number of the pipeline stages of the processing unit between n and m. The switching unit comprises an indicating unit for indicating whether the data processor is in a first operating condition or in a second operating condition, depending either on the frequency of the operation clock provided for the data processor or on the power source voltage supplied to the data processor, and a pipeline control unit for ordering a processing unit to operate in n stages under the first operation condition, and for ordering the processing unit to operate in m stages under the second operating condition.

Data processing having a variable number of pipeline stages

A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction 'MCSST D1' is decoded, the sum-product result register 6 outputs its held value to the path P1. The comparator 22 compares the magnitude of the held value of the sum-product result register 6 with the coded 32-bit integer '0x0000.sub.-- 00FF'. The polarity judging unit 23 judges whether the eighth bit of the value held by the sum-product result register 6 is 'ON'. The multiplexer 24 outputs one of the maximum value '0x0000.sub.-- 00FF' generated by the constant generator 21, the zero value '0x0000.sub.-- 0000' generated by the zero generator 25, and the held value of the sum-product result register 6 to the data bus 18.

Processor which can favorably execute a rounding process composed of

An information processing device, including a main processor and a coprocessor for processing data according to instructions stored in memory, which is composed of an instruction bus for transmitting instructions from memory to the main processor and coprocessor; a first bus used for transmitting data from the main processor to the coprocessor; a second bus used for transmitting data from the coprocessor to the main processor; instruction detecting means for detecting coprocessor calculation instructions out of the instructions received from memory; operand identifying means for identifying source registers and destination registers specified by operands in a detected instruction; data supplying means for supplying data from the identified source registers to the coprocessor via the first bus; data storing means for storing coprocessor calculation results in the identified destination registers; coprocessor instruction detecting means for detecting coprocessor calculation instructions out of all of the instructions received from the memory; and coprocessor instruction executing means for executing the coprocessor calculation instructions detected by the coprocessor instruction detecting means using data supplied by the first bus and for supplying the calculation result on the second bus.

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Osaka, Japan

Toru Morikawa