Nec Corporation

Oki Electric Industry Co., Ltd.

Lapis Semiconductor Co., Ltd.

Mitsubishi Chemical Corporation

Yokogawa Electric Corporation

Oki Semiconductor Co., Ltd.

Nec Toshiba Space Systems, Ltd.

Masahiro Ota, Director General, Technical Research and Development

Toru Mori

Shintaro Yamamichi

Atsushi Ochi

Akinobu Shibuya

Yuzo Shimada

Takao Yamazaki

Shinji Ito

Mitsuru Furuya

Makoto Saruya

Tadahiko Horiguchi

Shinji Abe

Kazuaki Utsumi

Naoki Oda

Hirokazu Tohya

Tsutomu Kaneko

Akira Okamoto

Yasuyuki Nakamura

Masao Okihara

Yoshimi Kubo

Yasushi Kinoshita

Tokuhito Sasaki

Shinobu Takehiro

Toshikazu Yamamoto

Shiro Yoshida

Yuji Kuno

Hiroshi Wabuka

Tetsuo Yoshimoto

Hideo Wada

Motohiro Munakata

Katsuya Kawano

Koichiro Nakase

Hitoshi Nimura

Toshio Akai

Osamu Yamakita

Mitsuyoshi Tsukada

Mitsuhiro Nagashima

Taku Shibaguchi

Souichiro Sugano

Hiroshi Ishikawa

Kenji Oonuki

Takao Yamakazi

A semiconductor device includes a semiconductor substrate and a first memory cell disposed on the semiconductor substrate. The first memory cell includes a first write and erasure transistor, a first read transistor, and a first charge transfer reduction transistor. The first write and erasure transistor controls data writing and erasing. The first read transistor controls data reading. The first charge transfer reduction transistor reduces injection of an electric charge to the first write and erasure transistor and the first read transistor.

Semiconductor memory with charge transfer reduction transistor

A semiconductor device, including: a first well of a first polarity formed in a semiconductor substrate; a source region and a drain region of a second polarity formed in the first well so as to be separated from each other by a predetermined spacing; an impurity region of the first polarity formed so as to surround the source region and the drain region; a first gate oxide film formed on the semiconductor substrate at a position between the source region and the drain region; a second gate oxide film formed on the first gate oxide film; a gate electrode formed on the second gate oxide film; and an impurity layer of the first polarity formed below the first gate oxide film.

Semiconductor device and semiconductor device fabrication method

A semiconductor device includes a semiconductor substrate; a first semiconductor region that includes an extension portion extending in a specific direction at a specific width as viewed along a direction orthogonal to the main surface; a second semiconductor region that is shaped to include a portion running along the extension portion of the first semiconductor region as viewed along the direction orthogonal to the main surface; a field relaxation layer that relaxes a field generated between the first semiconductor region and the second semiconductor region, that is formed on the second semiconductor region side of the main surface, and that is formed by a semiconductor layer; and a conductor that is connected to the second semiconductor region, and that has an end portion on the first conductor region side positioned within the range of the field relaxation layer.

Semiconductor device and semiconductor device manufacturing method

A non-volatile memory device includes a memory cell region which is formed on a semiconductor substrate to store predetermined information, and a peripheral circuit region which is formed on the semiconductor substrate. The memory cell region includes a gate electrode; and a charge storage layer, the charge storage layer being formed to be a notch or wedge shape having an edge extending into both sides of a bottom end of the gate electrode. The peripheral circuit region includes no charge storage layer therein.

Non-volatile memory device

In an Mn-containing perovskite oxide which is a conventional phase-change substance (AB)MnO, when the mixing amount x is increased, the transition temperature (Tc) is shifted to higher temperature side, but the slope of a change in the emittance become gentle and &#x394;&#x3b5; (&#x3b5; at higher temperature&#x2212;&#x3b5; at lower temperature) also become small. In the present invention, the compositional formula of the phase-change substance is the Mn-containing perovskite oxide represented by (AB)MnOwith 0&#x3c;y in which the Mn ratio is changed from stoichiometric composition, thereby shifting the transition temperature (Tc) to a higher temperature with the emittance characteristic thereof comparable to that of the phase-change substance having the composition which is not changed from stoichiometric composition.

Phase-change substance, thermal control device and methods of use thereof

To provide a catalyst for production of a polyester, a process for producing a polyester using the catalyst and a titanium-containing polyethylene terephthalate having excellent characteristics. A catalyst for production of a polyester, characterized by comprising at least (1) a Group 4A compound (hereinafter referred to as compound (1)), (2) a compound of at least one element selected from the group consisting of magnesium, calcium and zinc (hereinafter referred to as compound (2)) and an oxygen-containing organic solvent. A process for producing a polyester using this catalyst. A titanium-containing polyethylene terephthalate, having characteristics represented by the following (A), (B) and (C):

Catalyst for production of polyester, process for producing polyester using it and titanium-containing polyethylene terephthalate

A manufacturing method for an SOI semiconductor device includes creating transistors and an element isolation region on a semiconductor layer in an SOI substrate. The method also includes covering the transistors and the element isolation region with a first insulation film. The method also includes creating a first opening section which penetrates the first insulation film, element isolation region and a buried oxide film to expose the support substrate. The method also includes creating a first source interconnect, first drain interconnect and first gate interconnect which are electrically connected to the transistors, on the second insulation film. The method also includes forming dummy interconnects which are connected with these interconnects, and are electrically connected with the support substrate via the first opening section, on the second insulation film. The method also includes disconnecting the dummy interconnects to electrically insulate the first source interconnect, first drain interconnect and first gate interconnect from the support substrate.

Manufacturing method for SOI semiconductor device, and SOI semiconductor device

An LSI device includes a core region to which a first driving voltage is applied and an interface region to which a second driving voltage higher than the above first driving voltage is applied. The LSI device includes an SOI substrate and a device separation region for separating a SOI layer of the SOI substrate into the core region and the interface region. The thickness of the SOI layer of the core region is thinner than the thickness of the SOI layer of the interface region. The LSI device further includes first MOSFETs formed in the core region and in which the SOI layer of the core region is a fully depleted Si channel and second MOSFETs formed in the interface region and in which the SOI layer of the interface region is a fully depleted Si channel.

LSI device having core and interface regions with SOI layers of different thickness

A depolarizer includes a second birefringent plate having a thickness which continuously changes in a direction of an optical axis of the second birefringent plate; and a third birefringent plate having a thickness which continuously changes in a direction of 45 degree with respect to an optical axis of the third birefringent plate; wherein the second birefringent plate is stuck on the third birefringent plate so that a reduction direction of the thickness of the second birefringent plate and a reduction direction of the thickness of the third birefringent plate are opposite to each other.

Depolarizer and spectroscope and polychromater

A semiconductor device has an LSI device provided with a plurality of power supply line connection pads and ground line connection pad in a peripheral edge part of a circuit-formation surface, metal foil leadselectrically connected to each of the pads and adhered to the LSI device via an insulation layer, and decoupling capacitors mounted on one surface of the metal foil leads.

Semiconductor device with decoupling capacitors mounted on conductors

A thin film capacitor is provided with a substrate having a thickness equal to or more than 2 &mgr;m and equal to or less than 100 &mgr;m; a lower electrode on the substrate, which includes at least a highly elastic electrode and an anti-oxidation electrode on the highly elastic electrode; a dielectric thin film on the first lower electrode; and an upper electrode on the dielectric thin film; wherein the highly elastic electrode is made of a material having a Young's modulus higher than that of the anti-oxidation electrode.

Thin film capacitor, method for manufacturing the same and printed circuit board incorporating the same

A stacked capacitor which comprises: a dielectric layer; a two-dimensional array of terminal electrodes on at least one of first and second surfaces of the dielectric layer; first internal electrodes stacked in multi-levels in the dielectric layer, and the first internal electrodes being electrically connected to a power line second internal electrodes stacked in multi-levels in the dielectric layer, and the second internal electrodes being electrically connected to a ground line; vias in the dielectric layer, so that the terminal electrodes being electrically connected through the vias to the first and second internal electrodes.

Stacked capacitor and method of forming the same as well as semiconductor device using the same and circuit board using the same

A semiconductor device has an LSI device provided with a plurality of power supply line connection pads and ground line connection pad in a peripheral edge part of a circuit-formation surface, metal foil leads 5 electrically connected to each of the pads and adhered to the LSI device via an insulation layer, and decoupling capacitors mounted on one surface of the metal foil leads.

Semiconductor device and method for packaging same

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Tokyo, Japan

Toru Mori