Kabushiki Kaisha Toshiba

Toru Miyazaki

Kiyoyuki Kawai

Seijiro Yasuki

Toshiki Matsugami

An embodiment of the receiver of the invention includes an output unit to output program data to a recording appliance so as to record a copyright-protected service, a first copyright protective mechanism and a second copyright protective mechanism to protect copyright. The receiver further includes a system manager to detect whether or not a copyright protective mechanism of a recording appliance connected to the output unit is present and switch over between the first and second copyright protective mechanisms in accordance with the detection result to output the program data to the output unit.

Receiver, program recording controller, program recording control method and program recording system

A TV receiver with selectable signal processing systems in which main controller selects a proper signal processing system according to signal processing unit based on the results of monitoring the type and the number of the input signals by input signal monitor and the monitor result for user's request by signal display monitor . Main controller downloads the instruction program from program memory , and then transfers the instruction program to signal processing unit . Accordingly, signal processing unit performs one unit of the three-dimensional Y/C separation, two units of the two-dimensional Y/C separations or three units of the one-dimensional Y/C separation on the NTSC video signal.

TV receiver with selectable signal processing systems

Pattern data is generated in accordance with horizontal and vertical synchronizing components of a video signal. The pattern data and the video signal are stored in a memory. The video signal is written in an effective image period, while pattern data is written in other periods. Write and read addresses for the memory are generated in accordance with the horizontal and vertical synchronizing components of the video signal. Thus, pattern data is written over the video signal corresponding to the position at which display is required. Whether the output read from the memory is a video signal or pattern data is discriminated by a signal discrimination circuit in accordance with the read address. Pattern data and the video signal are individually signal-processed. In accordance with a result of the discrimination performed by the signal discrimination circuit, the output from a pattern data processor and the output from a video signal processor are switched and displayed by a monitor.

Digital image processor

A digital oscillator including an integrator for cumulatively integrating a specified signal and a controller responsive to a control signal for maintaining the output frequency of the integrator within a limit corresponding to the amplitude of the control signal.

Digital oscillator and color subcarrier demodulation circuit having the

A frame memory stores one-frame data of an input digital video signal and outputs the stored data as a one-frame delayed digital video signal. A first motion data generator receives the input digital video signal and the one-frame delayed digital signal from the frame memory and generates first motion data in accordance with the difference between these two signals. A data compander receives the one-frame delayed digital video signal from the frame memory, compands the data amount of the one-frame delayed digital video signal, and oututs the resultant signal. A sub-frame memory stores the output signa from the data compander and outputs the stored data as a two-frame delayed signal. A data expander receives the two-frame delayed output signal from the sub-frame memory, expands the two-frame delayed output signal to the original data amount, and outputs the resultant signal. A second motion data generator receives the input digital video signal and the two-frame delayed signal from the data expander, and generates second motion data in accordance with the difference between the two signals.

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Fukaya, Japan

Toru Miyazaki