Seiko Instruments Inc

Toru Machida

Yoshikazu Kojima

Yutaka Saitoh

Masanori Miyagi

Haruo Konishi

Kazuaki Kubo

Tetsuya Kaneko

Toru Shimizu

A MISFET is provided with a segmented channel comprising regions in which the channel is inverted by a first gate voltage and regions in which the channel is inverted by a second gate voltage. The MISFET is formed in a semiconductor substrate having a first conductivity type and the first inversion region of the channel has a first impurity concentration determined by the surface concentration of the substrate. The second inversion region of the channel has a second impurity concentration determined by doping an impurity to the region selected by a photolithographic process. The first and second inversion regions may be divided into a plurality of plane shapes and the threshold voltage of the MISFET is set to a desired value in accordance with the plane area ratio of the first and second inversion regions.

Semiconductor device and manufacturing method thereof

In a MISFET, areas where a channel surface of a channel region is inverted by a first gate voltage and areas where the channel surface is inverted by a second gate voltage are provided in the channel region of the MISFET in plane as components thereof. The channel region,having a first impurity concentration determined by a surface concentration of a P-type semiconductor substrate and a channel region,having a second impurity concentration determined by doping an impurity to the region selected by a pattern,of a mask for doping impurity by ion implantation and others are provided in a channel region of an N-type MOSFET on the P-type semiconductor substrate. The channel region,having the first impurity concentration and the channel region,having the second impurity concentration are divided into a plurality of plane shapes. The channel region of the same MOSFET may be structured by the plurality of plane shapes having the plurality of impurity concentrations as described above and a threshold voltage of the MOSFET may be readily set to a desired value in response to a plane area ratio of the area having the first impurity concentration and the area having the second impurity concentration, allowing to realize a high performance semiconductor integrated circuit device at low cost.

It is an object of the invention to provide a semiconductor memory integrated circuit wherein the sate of all of the memory cells in the memory array can be checked by measuring only one data output terminal. A means for interconnecting read signal buses is provided to connect the read signal buses to each other. A multiplicity of IC chips can be simultaneously measured and inspected even if the numbers of the drivers, comparators and DC measuring units, and the like available in the inspection apparatus used are limited.

Semiconductor memory integrated circuit

An object is to enable a semiconductor integrated circuit device to perform the second action, without waiting for the first action to finish after the first action starts. Aside from a resistor containing input signal pulses, an input signal pulses recognizing circuit is provided so that it detects signal input which activates the second action during the execution of the first action and controls driving with the result thereof. In a device such as EEPROM, CPU moves on the next action after writing operation starts. CPU checks periodically whether writing operation is being conducted or has finished, so that the processing ability of a whole device can be improved to the maximum.

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Chiba, Japan

Toru Machida