Nippon Hoso' Kyokai

Sanyo Electric Co., Ltd.

Nippon Conlux Co., Ltd.

Sony Corporation

Hitachi, Ltd.

Kabushiki Kaisha Nippon Coinco

Toru Kuroda

Osamu Yamada

Masayuki Takada

Koichi Yamazaki

Tomohiro Saito

Yoshikazu Tomida

Syugo Yamashita

Masafumi Saito

Shigeki Moriyama

Tadashi Isobe

Takahiro Okada

Makoto Sasaki

Tamotsu Ikeda

Yasunari Ikeda

Toshihisa Hyakudai

Kazuo Noda

Yasuyuki Kimura

Kenichi Tsuchida

Naohiko Iai

A frequency interleaving circuit frequency-interleaves main signals generated according to sound data by parameters set according to frequencies of transmission channels. A sub-signal generating circuit generates sub-signals for transmission control including pilot signals. Mapping circuits modulate the sub-signals by using pseudo-random sequences generated based on initial values of random codes set according to frequencies of transmission channels. The frequency-interleaved main signals and the sub-signals modulated by the mapping circuits are OFDM-modulated. Then, they are converted to the frequencies of the transmission channels. An increase of a dynamic range of transmission signals can be suppressed by controlling the initial values of random codes set.

Digital broadcasting apparatus

An error correcting decoder includes a flag memory (20) which stores a flag indicative of a success of an error correction for a bit. When a column direction error correction is to be performed, if a flag for a bit indicates a success, no error correction is performed for the bit. That is, an output of a majority logic circuit (78) is forcedly made invalid. In performing the column direction error correction, if the number of success packets in a first-time row direction error correction is smaller than a predetermined value and if the number of bits corrected by the column direction error correction becomes equal to or larger than a predetermined number, it is deemed as that the column direction error correction is unsuccessful. In performing a second-time row direction error correction, when a threshold value is equal to or larger than a predetermined value, the majority logic circuit determines with referring to a result of the column direction error correction, but without referring to the result when the threshold value is smaller than the predetermined value.

Error correcting decoder

A frame-synchronous reproducing circuit (10) includes a BIC status register (20) of six stages, and a BIC status signal (c) from each stage of the register is applied to a BIC pattern determination circuit (24) in which the BIC status signal (c) and a BIC changing pattern being stored in advance are compared with each other. If the both are coincident with each other, the BIC pattern determination circuit (24) applies a high-level signal to a JK flip-flop (26) via an OR circuit (48), whereby a high-level signal representing that frame synchronization has been settled is outputted from the JK flip-flop (26).

Frame-synchronous reproducing circuit

In an error correction circuit, when a data loss is detected, substitute data comprising all bits of '1' or '0' are generated during a data loss period and substituted for the lost data for the data loss period. Thereafter, the whole data containing the substitute data are decoded in a predetermined error correction system to generate corrected data.

Error correction circuit which substitutes bits into data stream during

A write once type information recording medium having a recording format that includes sectors. Each Sector includes x pieces of p-bit frames. Each frame contains an f-bit synchronization signal region and a d-bit data region. Each bit of at least one x-bit packet in which a v-bit error correction code has been added to u-bit data, is distributed to each one of the data regions of the x pieces of frames. This makes it possible for the write once type information recording medium to have an increased data storage efficiency and an effective error correction capability for a burst error.

Write once type information recording medium, method and apparatus for

Method and apparatus for transmitting an information signal generate a plurality of block signals on the basis of the information signal, generate a plurality of parity block signals on the basis of the plural data block signals, generate a frame signal containing the plural data block signals and the parity block signals, and send out the frame signal. Each of the data block signals includes a first block synchronizing signal indicating the start of the data block signal, a data signal containing the information signal and a first parity signal derived by encoding the data signal. Each of the parity block signals incudes a second block synchronizing signal indicating the start of the parity block signal, a second parity signal and a third parity signal. Bit signals located at same bit positions in the respective second parity signals are derived by encoding bit signals located at the same positions in the respective data signals. Bit signals located at same bit positions in the respective third parity signals are derived by encoding the bit signals located at the same bit positions in the respective first parity signals or alternatively the third parity signal in each parity block signal is derived by encoding the second parity signal in each parity block signal.

Methods and apparatuses for transmission and reception of information

A digital signal transmission using OFDM modulation scheme in which the valid transmission data can be reproduced without requiring a recovery of the carriers at a receiver side. On a transmitter side, the transmission data sequence in which predetermined reference data for each carrier are placed among valid transmission data is modulated according to an orthogonal frequency division multiplexing (OFDM) modulation scheme using a plurality of carriers and obtained OFDM transmission signals are transmitted. On a receiver side, the received OFDM transmission signals are demodulated to obtain received data sequence containing valid received data and received reference data, and the valid transmission data are estimated from the received data sequence according to the valid received data, the received reference data, and the predetermined reference data for each carrier.

Method and apparatus for digital signal transmission using orthogonal

An error correction coding and decoding circuit for digitally coded information in which a majority difference set cyclic code is used to apply error correction coding and decoding to a data signal having data bits suitably assigned to information bits and parity bits, characterized in that a clock signal (CLKC) for the internal operation of the circuit, a data load clock signal for loading data onto the circuit, and a data read clock signal for reading data from the circuit are delivered from an external circuit provided separately from the error correction coding and decoding circuit.

Error correction coding and decoding circuit for digitally coded

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Tokyo, Japan

Toru Kuroda