Toshiba Memory Corporation

Kioxia Corporation

Toru Katagiri

Konosuke Watanabe

Kenji Funaoka

Takuya Haga

Yukimasa Miyamoto

Shoji Sawamura

A memory system includes a non-volatile memory and a controller. The controller controls writing of data to the non-volatile memory or reading of data from the non-volatile memory, in response to a command from at least one host. The controller performs command fetching by calculating for each of a plurality of queues, a remaining processing amount, which is an amount of processing remaining for one or more commands previously fetched therefrom, selecting a queue based on the remaining processing amounts calculated for the plurality of queues, and fetching a new command from the selected queue.

Memory system and method of fetching command

A memory system, which is connectable to a host, includes a non-volatile memory and a controller configured to store data in the non-volatile memory and in a memory region within the host and read the data from the memory region within the host. The controller includes a first encoding/decoding circuit configured to execute encoding/decoding with a first encoding scheme, a second encoding/decoding circuit configured to execute encoding/decoding with a second encoding scheme having a higher error correcting capability than an error correcting capability of the first encoding scheme, an encoding scheme selecting circuit configured to select an encoding/decoding circuit from the first encoding/decoding circuit and the second encoding/decoding circuit to perform encoding of data to be stored in the memory region, based on information about the data read from the memory region.

Memory system

According to one embodiment, a memory system is connectable to a host device including a first memory. The memory system includes a memory controller and a second memory in which data from a host device is stored. The memory controller includes a third memory, a first unit and a second unit and has a first space. The first unit designates a first address in the first space. The second unit converts, by using a conversion table, the first address into a second address in a first area of the first memory. The conversion table includes a plurality of layers and includes a first conversion table of a top layer and a second conversion table of a layer lower than the first conversion table. The first conversion table is stored in the third memory. The second conversion table is stored in a second area of the first memory.

Growing community of inventors

Sagamihara Kanagawa, Japan

Toru Katagiri