Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Daikin Industries, Ltd.

Panasonic Intellectual Property Management Co., Ltd.

Matsushita Electrical Industrial Co., Ltd.

Matsushta Electric Co., Ltd.

Toru Iwata

Hironori Akamatsu

Hiroyuki Yamauchi

Takashi Hirata

Takefumi Yoshikawa

Satoshi Takahashi

Hirokazu Sugimoto

Osamu Shibata

Yoshiyuki Saito

Yutaka Terada

Tsuyoshi Ebuchi

Shiro Dosho

Shiro Sakiyama

Keiichi Kusumoto

Hiroshi Suenaga

Hisakazu Kotani

Yusuke Tokunaga

Ryogo Yanagisawa

Masayuki Toyama

Yoshihide Komatsu

Yukio Arima

Noriaki Takeda

Takaharu Yoshida

Kyoko Hirata

Kazuko Nishimura

Kiyoshi Morimoto

Makoto Kojima

Kiyoyuki Morita

Akira Matsuzawa

Michihito Ueda

Masahiro Fukui

Kenji Toyoda

Shinya Miyazaki

Jun Kajiwara

Naoshi Yanagisawa

Yasuyuki Doi

Yasunori Okamoto

Yoshimasa Kikuchi

Hironobu Teraoka

Tetsuyuki Fukushima

Masashi Kamada

Akinori Shinmyo

Yuji Yamada

Masahito Higashida

Masaomi Toyama

Zhiming Zheng

Shimei Tei

Syuji Kato

Masakazu Hirai

Anan Takada

Makoto Hattori

Keijiro Umehara

Tomoko Chiba

Tsuyoshi Hiraki

Makoto Miyake

Wataru Itoh

Ryoichi Suzuki

Kunihiko Miyake

Shoichiro Tada

Shinya Murakami

Manabu Kawabata

Hideki Yoshii

Takeyoshi Kimura

Mishihisa Tsutahara

A centrifugal blower includes an impeller, and a scroll casing. The impeller draws in gas through an opening in a side surface and sends out the gas in a centrifugal direction. The scroll casing includes an inlet, an outlet, a peripheral wall arranged along an impeller outer circumference, and a tongue that guides the gas flowing along the peripheral wall to the outlet. The peripheral wall includes a first planar portion extending continuously from the tongue, and a second planar portion located at a position advanced from the first planar portion in a rotation direction of the impeller. The peripheral wall is arranged so that a clearance is minimal at the second planar portion. The clearance is a difference between distances from a center of the impeller to an inner surface of the peripheral wall and to an outer surface of the impeller in a passage along the peripheral wall.

Centrifugal blower

An interchannel skew adjustment circuit adjusts signal skew between a first channel and a second channel. The circuit includes a phase adjustment circuit configured to receive a signal of the first channel, delay the signal by a discretely variable delay amount, and output a delayed signal; a channel coupling circuit configured to receive the signal output from the phase adjustment circuit and a signal of the second channel, and detect a phase difference between these two signals; and a controller configured to control the delay amount in the phase adjustment circuit based on a result detected by the channel coupling circuit. This interchannel skew adjustment circuit adjusts the interchannel signal skew only at a sender or a receiver, thereby reducing the circuit area and the power consumption.

Interchannel skew adjustment circuit

A crossflow fan includes a rotary impeller formed by curved blades. Each of the bladeshas an outer peripheral edgeclose to the centrifugal side of the impeller and an inner peripheral edgeclose to the rotation axis side of the impeller. A plurality of cutoutsare formed in the outer peripheral edgeand spaced apart at predetermined intervals. Dimplesfor changing a boundary layer from a laminar flow to a turbulent flow are formed in a negative pressure surfaceof each bladein the vicinity of the outer peripheral edgeto prevent the gas flowing around the bladefrom separating from the blade

Crossflow fan and air conditioner provided with same

In a signal electric potential conversion circuit, a capacitor has one end receiving an input signal CIN, and the other end connected to a termination node N. A conversion circuit receives a potential IN of the termination node N. A connection element is provided between a power supply VDDH and the termination node N, and an impedance of the connection element is reduced when the potential IN is lower than a first potential. Another connection element is provided between the termination node Nand a ground power supply, and an impedance of the connection element is reduced when the potential IN is higher than a second potential.

Signal electric potential conversion circuit

A centrifugal fan has a circular main plate driven and rotated by a motor rotary shaft, a plurality of blades fixed to an outer circumferential portion of the main plate and spaced apart at predetermined intervals in a circumferential direction of the main plate, and a side plate attached to ends of the blades opposite to the main plate. An air inlet port is formed at the center of the side plate. The side plate inclines outward in centrifugal directions from the air inlet port and has an arcuate cross section with a predetermined radius of curvature. A dead water region reducing space is formed between the blades and the side plate. The dead water region reducing space forms a smooth flow between the two surfaces of each blade, bringing about desirable blade performance.

Centrifugal fan

An input processing circuit decodes a digital video signal selected by an input signal selector. Decryption circuits each decrypt the encryption of a video signal output from the input processing circuit, and generate an authentication key of the encryption. A video signal selector selects and outputs one of the video signals output from the decryption circuits, to a monitor. The decryption circuits each include a pseudo-signal generation circuit which extracts information from the video signal, and based on the extracted information, generates a pseudo-video signal.

Video input device and video display system

A driver supplies data signal via a supply node. A voltage-relaxing transistor has a source connected to the supply node of the driver, a drain connected to a signal node connected to a signal line, and a gate to which the voltage at the signal node is applied.

Data communication circuit, transmission apparatus, reception apparatus, and transmission/reception system

A comparison period detecting unit () defines, as a comparison period, a period between a rising edge of a first clock signal and a rising edge of a second clock signal, and detects the presence or absence of transition of a data signal during the comparison period. A phase relationship detecting unit () detects a phase relationship between the data signal and a reference clock signal, and outputs a result of detection of the phase relationship when the comparison period detecting unit () detects transition of the data signal during the comparison period.

Phase comparator, phase comparison device, and clock data recovery system

It is an object of the invention to inhibit a drop in the data transmission efficiency due to the transmission of an interrupt signal. The invention provides a signal transmission method that is characterized in that a reception side and a transmission side partition data into a plurality of data fragments and send and receive the plurality of data fragments over at least two transmission lines, in that the transmission side transmits first data fragments of the plurality of data fragments over a first transmission line of the transmission lines, transmits data packets that include header information, a second data fragment that has the same bit length as the first data fragments, and footer information over a second transmission line other than the first transmission line, and transmits the first data fragments and the second data fragments in synchronization, and in that an interrupt signal for controlling the transmission side is transmitted from the reception side to the transmission side in a time slot that is an interval between first data fragments that are adjacent on the first transmission line.

Method, device, and system for transmitting data fragments over multiple transmission lines and techniques for stopping data transmission

The charge pump circuit includes: a first switch for controlling either one of push operation and pull operation based on a first control signal; a current mirror circuit composed of a transistor different in attribute from the first switch; and a second switch composed of a transistor same in characteristic as a transistor constituting the first switch, for controlling input of a current into the current mirror circuit based on a second control. The other operation, the push operation or the pull operation, is performed with a current output from the current mirror circuit.

Charge pump circuit

A semiconductor integrated circuit (D) for receiving a parallel data signal and a first clock signal and outputting a serial data signal and a second clock signal, wherein a first clock generation circuit () produces a third clock signal obtained by multiplying the first clock signal by X/Y. A second clock generation circuit () has a variable transmission characteristic, and produces a fourth clock signal obtained by multiplying the third clock signal by N. A parallel/serial conversion section () converts the parallel data signal, which has been converted by a scaler (), to the serial data signal in synchronism with the fourth clock signal. A frequency divider () produces a fifth clock signal obtained by dividing a frequency of the fourth clock signal by N. A selector () selectively outputs, as the second clock signal, one of the third and fifth clock signals.

Semiconductor integrated circuit and transmitter apparatus having the same

A phase comparison process in a timing recovery process for high-speed data communication defines a data window and compares the phase of a clock in the window with the phase of an edge of data so as to realize a parallel process, wherein the phase comparison and the process of determining whether a data edge lies within the window are performed in parallel to each other, and the phase comparison result is output only if the data edge lies within the window. With this configuration, it is possible to perform an accurate phase comparison process with no errors without requiring high-precision delay circuits.

Phase comparator and regulation circuit

The data receiver device includes: a bit phase synchronizing circuit () for performing phase adjustment of a received data signal to set a predetermined phase relationship between the data signal and a corresponding clock signal; and a state detection circuit () for outputting a detection signal once detecting that the data signal inputted into the bit phase synchronizing circuit () is in a stable state based on a data signal phase-adjusted by the bit phase synchronizing circuit () and a corresponding clock signal. The bit phase synchronizing circuit () initializes the phase adjustment of the data signal when receiving the detection signal.

Data receiver device and data transmission/reception system

An object of the present invention is to realize reduction in an area of an output stage driver in an interface circuit that switches between two transmission systems. The interface circuit has two driver circuits and a drive control circuit that can switch between two driving systems that are a voltage driving system and a current driving system. The two driver circuits are connected to a power supply potential via the drive control circuit. Two input signals and inverted logic signals of the input signals are inputted via a selection circuit. According to a control signal inputted into the drive control circuit, the interface circuit switches between the voltage-driving type single-ended transmission system and current driving type differential transmission system.

Interface circuit that can switch between single-ended transmission and differential transmission

An object of the present invention is to provide a technique to improve the data transmission efficiency which allows correct reception of the data at the same time. A removable memory device that transmits/receives data to and from a host terminal, which includes: a clock reception section that receives a transmission/reception clock, which is used for transmitting/receiving data between the host terminal and the removable memory device, from the host terminal; a phase synchronization pattern generation section that generates a phase synchronization pattern, which is for adjusting a phase of internal reception clock which the host terminal incorporates for receiving data from the removable memory device, based on the transmission/reception clock; and a transmission section that transmits the generated phase synchronization pattern to the host terminal, and in which the phase synchronization pattern includes a first level signal which lasts for at least two cycles, and a second level signal which follows the first level signal and lasts for one cycle, is provided.

Removable memory device, phase synchronizing method, phase synchronizing program, medium recording the same, and host terminal

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Osaka, Japan

Toru Iwata