Cirrus Logic Inc.

Toru Ido

Gordon James Bates

John Paul Lesso

David Paul Singleton

John Anthony Breslin

The present disclosure relates to driver circuitry for driving a piezoelectric transducer. The circuitry comprises: a power supply; a reservoir capacitance; switch network circuitry; and control circuitry. The control circuitry is configured to control operation of the switch network circuitry so as to charge the reservoir capacitance from the power supply and to transfer charge between the reservoir capacitance and the piezoelectric transducer.

Driver circuitry for piezoelectric transducers

This application relates to computing circuitry () for analogue computing. A plurality of current generators () are each configured to generate a defined current (I, I, . . . I) based on a respective input data value (D, D, . . . D). A memory array (), having at least one set () of programmable-resistance memory cells (), is arranged to receive the defined currents from each of the current generators at a respective signal line (). Each set () of programmable-resistance memory cells () includes a memory cell associated with each signal line that, in use, can be connected between the relevant signal line and a reference voltage so as to generate a voltage on the signal line. An adder module () is coupled to each of the signal lines to generate a voltage at an output node () based on the sum of the voltages on each of the signal lines.

Computing circuitry

This application relates to methods and apparatus for computing, especially to circuitry for performing computing, at least partly, in the analogue domain. The circuitry () comprises a plurality of memory cells (), each memory cell having first and second paths between an electrode () for receiving an input current and respective positive and negative electrodes () for outputting a differential-current output. Memristors () are located in the first and second paths. The memory cells are configured into sets () of memory cells, the memory cells of each said set being connected so as to provide a differential current set output that corresponds to a combination of the cell outputs of all of the memory cells of that set. For each set, at least some of the memory cells of that set are configured to receive a different input current to other memory cells of that set.

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Edinburgh, United Kingdom

Toru Ido