Fujitsu Corporation

Toru Hikichi

Junlu Chen

Shuji Yamamura

Hideaki Tomatsuri

Koichi Onodera

Kenta Umehara

An arithmetic processing device includes: an arithmetic circuit that executes an instruction; a first cache which is coupled to the arithmetic circuit and which has a plurality of first entries each including a first tag region and a first data region that holds cache line data; a second tag region; a processor which controls the first cache based on information held in the second tag region; and a second cache which is coupled to the first cache via the processor and which includes a plurality of second entries each of which includes a third tag region and a second data region that holds cache line data. The second tag region includes a first region that holds first information which specifies whether or not the second data region holds cache line data which has the same address as the address of cache line data held in the first data region.

Arithmetic processing device and arithmetic processing method

An arithmetic processor including a plurality of core groups each including a plurality of cores and a cache unit, a plurality of home agents each including a tag directory and a store command queue and a store command queue. The store command queue enters the received store request to the entry queue in order of reception, the cache unit stores the data of the store request in a data RAM. The store command queue sets a data ownership acquisition flag of the store request to valid when obtaining a data ownership of the store request and issues a top-of-queue notification to the cache control unit when the flag of the top-of-queue entry is valid. In response to the top-of-queue notification, the cache unit update a cache tag to modified state and issue a store request completion notification.

Arithmetic processor and method for operating arithmetic processor

An apparatus includes: a processor core to execute an instruction; a first cache to retain data used by the processor core; and a second cache to be coupled to the first cache, wherein the second cache includes a data-retaining circuit to include storage areas to retain data, an information-retaining circuit to retain management information that includes first state information for indicating a state of data retained in the data-retaining circuit, a state-determining circuit to determine, based on the management information, whether requested data that is requested with a read request from the first cache is retained in the data-retaining circuit, and an eviction-processing circuit to, where the state-determining circuit determines the requested data not to be retained in the data-retaining circuit with no enough space in the storage areas to store the requested data, evict data from the storage areas without issuing an eviction request based on the read request.

Operation processing device, information processing apparatus, and control method for operation processing device

An operation processing device including: processors, first cache corresponding to each processors; and a second cache shared by the processors, wherein the second cache includes; a data retaining unit that retains data, a first information retaining unit that retains first management information of data in the first cache, a second information retaining unit that retains second management information of data in the data retaining unit, a classifying unit that classifies a request performed by referencing the first management information and not referencing the second management information as a first type request and classifies a request performed by referencing the second management information as a second type request, a second processing unit that references the second management information to perform the second type request, and a first processing unit that references the first management information and does not reference the second management information to perform the first type request.

Operation processing device having hierarchical cache memory and method for controlling operation processing device having hierarchical cache memory

A computational processing device includes: a computational-processor that outputs access requests to a storage device; a plurality of request-holding-units that respectively hold access requests output by the computational processor according to individual access types, the access types being types of access requests; an arbitration-unit that arbitrates access requests held in the plurality of request holding units; a buffer-unit that includes a plurality of entries that hold data; and a buffer-controller that causes one of the plurality of entries to hold data output by the storage device in response to an access request arbitrated by the arbitration unit, on the basis of a result of comparing, for each access type, a count value that counts, for each access type, the number of entries holding data from among the plurality of entries against a maximum value for the number of entries made to hold data for each access type.

Computational processing device including request holding units each provided for each type of commands, information processing device including request holding units each provided for each type of commands, and method of controlling information processing device

A processor includes: a processing unit that has a first unit; a second unit that holds part of the data held by the first unit; a third unit that receives from the processing unit a first request including first attribute information for obtaining a first logical value and a second request including second attribute information for obtaining a second logical value and that holds the first request until receiving a completion notification of the first request or holds the second request until receiving a completion notification of the second request; and a control unit that receives the first and second requests from the third unit and, replaces the first attribute information by the second attribute information when data of the addresses corresponding to the first and second request are not in the second unit, and supplies the completion notification for the second request to the first unit.

Processor and method of control of processor

A common L2 cache unit of a CPU constituting a multicore processor, in addition to a PFPORT arranged for each CPU core unit, has a common PFPORT shared by the plurality of the CPU core units. The common PFPORT secures an entry when the prefetch request loaded from the PFPORT into a L2 pipeline processing unit fails to be completed. The uncompleted prefetch request is loaded again from the common PFPORT to the L2 pipeline processing unit.

Arithmetic processing apparatus and method of controlling the same

The information processing device of the present invention stores the branch history information of a fetched instruction. When branch prediction fails, BHR information used for the branch prediction is restored using this stored branch history information. Thus, even when branch prediction fails, BHR information can be accurately restored. Accordingly, prediction accuracy can be improved.

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Inagi, Japan

Toru Hikichi