Hitachi, Ltd.

Hitachi America, Ltd.

Renesas Technology Corp.

Nippon Telegraph and Telephone Public Corporation

Renesas Electronics Corporation

Hitachi Device Engineering Co., Ltd.

Toru Baji

Koki Noguchi

Toshihisa Tsukada

Atsushi Kiuchi

Shiro Baba

Yasushi Akao

Tetsuya Nakagawa

Hideaki Yamamoto

Yuji Hatano

Norio Koike

Hiroshi Ohsuga

Hironobu Hasegawa

Yasuhiro Sagesaka

Akira Sasano

Yukio Takasaki

Yasuo Tanaka

Shinya Ohba

Eiichi Maruyama

Hajime Akimoto

Iwao Takemoto

Masaharu Kubo

Kouki Noguchi

Tadaaki Hirai

Toshiaki Masuhara

Shusaku Nagahara

Sachio Ishioka

Yasuharu Shimomoto

Motonobu Tonomura

Hirotsugu Kojima

Yukio Nakano

Toshiyuki Akiyama

Shigeru Shimada

Tatsuji Matsuura

Yoshinori Imamura

Yoshimune Hagiwara

Kenji Kaneko

Haruo Matsumaru

Haruhisa Ando

Shiro Tanabe

Chushirou Kusano

Saburo Ataka

Toshiro Tsukada

Masafumi Miyamoto

Kouichi Seki

Eizou Ebisui

Hidenori Inouchi

Nario Sumi

Stephen G Haigh

Yuji Izawa

Hisao Ohta

Naohiko Koizumi

A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core () integrated as a single bus master, an integrated external bus interface () and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.

Terminal apparatus

A built-in memory is divided into the following two types: first memoriesandand second memoriesand, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU corecan simultaneously transfer two data values from the built-in memory to a DSP engine. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU corecan access an external memory in parallel with the access to the second memoriesandand the first memoriesand

Microcomputer

In microcomputers and digital signal processors in which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on one and the same chip, an increase in the number of processing steps caused by differing types of data handled by the calculators is prevented, thereby enhancing the efficiency of the digital signal processing.

Data processing device having a central processing unit and digital signal processing unit

A low cost, a low power consumption and a small size are three very important factors for a mobile communication terminal. A great problem is posed by the conventional technique using a DSP and a CPU independent of each other which requires two external memory systems. Also, two peripheral units are required for data input and output of the DSP and CPU. As a result, an extraneous communication overhead occurs between the DSP and the CPU. The invention realizes a mobile communication terminal system by a DSP/CPU integrated chip comprising a DSP/CPU core ( ) integrated as a single bus master, an integrated external bus interface ( ) and an integrated peripheral circuit interface. The memory systems and the peripheral circuits of the DSP and the CPU can thus be integrated to realize a mobile communication terminal system low in cost and power consumption and small in size.

Apparatus has a microprocessor including DSP and a CPU integrated with each other as a single bus master

A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and

Microprocessor having a DSP and a CPU and a decoder discriminating between DSP-type instructions and CUP-type instructions

A built-in memory is divided into the following two types: first memories and and second memories and , and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core can simultaneously transfer two data values from the built-in memory to a DSP engine . Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core can access an external memory in parallel with the access to the second memories and and the first memories and

Terminal

In microcomputers and digital signal processors in which a central processing unit for controlling the entire system and a digital signal processing unit having a product sum function required to process digital signals efficiently are mounted on one and the same chippthis invention prevents an increase in the number of processing steps caused by differing types of data handled by the calculators, thereby enhancing the efficiency of the digital signal processing. The digital signal processing unit is made a calculation unit that handles fixed-point data, and an instruction calling for execution of a fixed-point data calculation is provided separately from the conventional integer calculation instruction. When, in the data transfer between the digital signal processing unit and memories or external circuits, data shorter in bit length than the calculation precision is transferred, the calculation unit has a function to input and output data to and from the higher-order side of the register in which the data is stored and the fixed point data transfer instruction is provided separately from the conventional integer data transfer instruction. This invention can eliminate additional correction processing necessitated when the integer data processing unit is made to execute the digitalsignal processing.

System for maintaining fixed-point data alignment within a combination

A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.

A digital signal processor that includes an execution unit, a condition code register, a program memory, a program control unit, and an instruction decoder. The program memory stores a sequence of instruction words and includes an instruction word that has at least one field that identifies a data processing operation to be performed by the execution unit. The instruction word also includes a condition code field that identifies a predefined condition and also identifies whether said condition code register should be updated when the data processing operation is performed by the execution unit. The program control unit outputs an instruction address to the program memory so as to select the instruction word in the program memory. The instruction decoder decodes the selected instruction word. It includes decoder circuitry for decoding the at least one field to generate control signals for controlling the execution unit to perform the specific data processing operation. The execution unit includes means for generating a current condition code flag if a corresponding predefined condition occurs when the execution unit performs the current data processing operation in response to the control signals. The instruction decoder further includes condition code decoder circuitry for decoding the condition code field to generate a control signal for enabling and disabling the condition code register to store the current condition code flag in accordance with the condition code field's value.

Digital signal processor and associated method for conditional data

A digital signal processor (DSP) provides an improvement in the interfacing and sharing of external memory devices. Specifically, the digital signal processor is provided with a parallel interface for communicating with external memory devices, a chip select decoder located on-chip for selectably enabling external memory devices, and a wait status controller for holding processor operation until the selected memory device is ready. The memory architecture is configurable for internal or external wait state generation and memory sharing with other DSPs so that a plurality of varying speed memory devices may be accessed. The chip select decoder includes a programmable register for storing a mode configuration word for defining a plurality of external memory configurations.

Digital signal processor with on-chip select decoder and wait state

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Inagi, Japan

Toru Baji