Nec Corporation

Renesas Electronics Corporation

Nec Electronics Corporation

Denso Corporation

Toyota Tsusho Corporation

Toru Awashima

Takao Toi

Masato Motomura

Taro Fujii

Koichiro Furuta

Noritsugu Nakamura

Kenichiro Anjo

Yoshikazu Yabe

Hirokazu Kami

Yoshinosuke Kato

Toshiro Kitaoka

Shunsuke Takahashi

Toshirou Kitaoka

Masayoshi Terabe

Akira Miki

Yoshitaka Izawa

Kouichirou Furuta

Yoshiyuki Miyazawa

Hirotaka Irie

Wongpaisarnsin Goragot

Shiowattana Dungjade

An ising solver system that searches an optimal route of a vehicle from plural routes passing through plural locations. In the ising solver system, the search of the optimal route uses a Hamiltonian. The Hamiltonian includes an equation representing an interaction between Quadratic Unconstrained Binary Optimization (QUBO) variables depending on a relation between a departure location and an arrival location or capacitated variable of the ising solver. The capacitated variable corresponds to one of the QUOBO variables and includes a variable constraint, and the location-to-location travel step number corresponds to an accumulated movement time of the vehicle.

Ising solver system

A behavioral synthesis device include a profile unit that implements an electronic circuit at a reconfigurable hardware based on a first register transfer level description generated by a behavioral synthesis unit, actuates the implemented electronic circuit, and causes the electric circuit to output profile information from the actuated electronic circuit; and an optimizer that generates optimization information for optimizing a behavioral synthesis carried out by the behavioral synthesis unit based on the profile information that the profile unit causes the electric circuit to output, and outputs the generated optimization information to the behavioral synthesis unit, wherein the behavioral synthesis unit acquires a first behavioral level description, and subjects the acquired first behavioral level description to behavioral synthesis and generates the second register transfer level description based on the optimization information outputted by the optimizer.

Behavioral synthesis device, behavioral synthesis method, and computer program product

A delay library generation apparatus, associated control method, and associated program are provided. The delay library generation apparatus comprises a storage device which stores architecture information of a logic element array, layout data of an overall programmable logic device, a netlist of the overall programmable logic device, and a wiring route extraction unit which refers to the storage device and extracts wiring route information regarding a wiring route section based on the architecture information. Moreover, the delay library generation apparatus comprises an analyzing unit which analyzes the layout data of the logic device and extracts parameters of a parasitic element and a crosstalk between adjacent interconnections. The delay generation apparatus further comprises a delay calculation unit which calculates delay data based on the extracted parameters and a delay library generation unit which generates a delay library of the logic device based on the wiring route information and the delay data.

Delay library generation apparatus and method based on wiring arrangements

A reconfigurable device comprises a plurality of processing elements, a main memory unit that stores plural pieces of circuit configuration information, a cache unit that caches circuit configuration information forwarded to at least one of the processing elements from the main memory unit, and a cache control unit that controls forwarding of circuit configuration information from the cache unit to the processing element. The cache control unit selects circuit configuration information which must be forwarded to each processing element. When the selected circuit configuration information is not stored in the cache unit, the cache control unit reads out the circuit configuration information from the main memory unit, stores the read-out circuit configuration information in the cache unit, and sends forward the circuit configuration information to the processing element from the cache unit.

Reconfigurable device

A behavioral synthesis apparatus includes a acquisition unit, a scheduling unit and a generation unit. The acquisition unit acquires a behavioral level description describing an operation of a semiconductor integrated circuit. The scheduling unit separates the acquired behavioral level description into N stage descriptions, and makes a schedule in such a way that input/output operations and computations among the N stage descriptions are pipelined. The generation unit generates a register transfer level description based on the N stage descriptions and a result of scheduling performed by the scheduling unit in such a way as to form stage circuits respectively corresponding to the N stage descriptions and a state control circuit which controls possible 2N&#x2212;1 stage control states of the semiconductor integrated circuit. The generation unit generates the register transfer level description in such a way as to inhibit the operation of a stage circuit which need not be operated.

Behavioral synthesis apparatus, behavioral synthesis method, and computer readable recording medium

A multiplicity of processor elements that are arranged in rows and columns individually execute data processing in accordance with instruction codes that are individually set as data and supply event data as output. A state control unit is composed of a plurality of units that successively switch the instruction codes of the multiplicity of processor elements in accordance with a computer program and the event data, these state control units communicating with each other to realize linked operation as necessary. An event distributing means distributes event data to this plurality of state control units that intercommunicate to realize linked operation, whereby the plurality of state control units can realize linked operation to control a large-scale state transition.

Array-type processor having plural processor elements controlled by a state control unit

A reconfigurable integrated circuit includes a plurality of function blocks and a plurality of programmable switches to switchably connect between function blocks included in the plurality of function blocks. The plurality of function blocks each includes at least one operation unit or one memory unit. The plurality of function blocks each includes at least one data input port connected to at least on of the plurality of programmable switches and at least one data output port connected to at least one of the plurality of programmable switches. Further, at least a pair of function blocks included in the plurality of function blocks is connected without intervening the programmable switch and data being output from a direct output port included in one of the pair of function blocks can be input to a direct input port included in the other of the pair of function blocks.

Switch coupled function blocks with additional direct coupling and internal data passing from input to output to facilitate more switched inputs to second block

A configuration information writing apparatus for writing configuration information defining a logical configuration of a logic circuit device into the logic circuit device to change the logical configuration thereof, the apparatus comprising: a difference extracting unit that acquires plural pieces of configuration information and extracts differences between each of the acquired plural pieces of configuration information; a differential relation generating unit that generates a differential relation indicating a relation of the differences between each of the plural pieces of configuration information based on the differences extracted by the difference extracting unit; and an order information generating unit that generates order information specifying an order of writing the configuration information from the relation of the differences indicated by the differential relation generated by the differential relation generating unit.

Configuration information writing apparatus, configuration information writing method and computer program product

A data processing device for debugging code for a parallel arithmetic device that includes a plurality of data processing circuits arranged in a matrix and that causes, for each operating cycle, successive transitions of operation states in accordance with object code includes: operation execution means for causing the parallel arithmetic device to execute state transitions by means of the object code; device halt means for temporarily halting the state transitions for each operating cycle; a result output means for reading and supplying as output at least a portion of held data, connection relations, and operation commands of the plurality of data processing circuits of the halted parallel arithmetic device; a resume input means for receiving as input a resume command of the state transitions; and an operation resumption means for causing the operation execution means to resume the state transitions upon input of a resume command.

Data processing system for debugging utilizing halts in a parallel device

A multiplicity of processor elements, which both individually execute data processing in accordance with instruction codes that have been set as data and for which mutual connection relations are switch-controlled, are arranged in matrix form, and the instruction codes of this multiplicity of processor elements are successively switched by a state control unit. The state control units are composed of a plurality of units that intercommunicate to realize linked operation, and the multiplicity of processor elements is divided into a number of element areas that corresponds to the number of state control units. The plurality of state control units are arranged for each of the plurality of element areas and are connected to the processor elements, whereby the plurality of state control units can individually control a plurality of small-scale state transitions, or the plurality of state control units can cooperate to control a single large-scale state transition.

Array-type processor having state control units controlling a plurality of processor elements arranged in a matrix

An object code for sequentially switching contexts of processing circuits arrayed in a matrix in a parallel operation apparatus is generated from a general source code descriptive of operation of the parallel operation apparatus. A Data Flow Graph (DFG) is generated from the source code descriptive of operation of the parallel operation apparatus according to limiting conditions, registered in advance, representing a physical structure, etc. of the parallel operation apparatus, and scheduled in a Control Data Flow Graph (CDFG). An Register Transfer Level (RTL) description is generated from the CDFG, converting a finite-state machine into an object code and converting a data path into a net list. An object code of the processing circuits is generated in each context from the net list.

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Tokyo, Japan

Toru Awashima