Infineon Technologies Ag

Infineon Technologies North America Corp.

Siemens Aktiengesellschaft

Infineon Technologies LLC

Infineon Technology Ag

Infienon Technologies Ag

Torsten Partsch

Thomas Hein

Patrick Heyne

Thilo Marx

Stefan Dietrich

Jennifer Faye Huckaby

Johnathan Edmonds

Christian Weis

George William Alexander

Peter Schr&ouml;gmeier

Michael Bernhard Sommer

Sabine Kieser

Michael Markert

Peter Schroegmeier

David Herbert

Ben Heilmann

Tao Tian

Alessandro Minzoni

Thoai-Thai Le

Jonghee Han

David SuitWai Ma

Thoai Thai Le

Christopher Kunce

Biju Velayudhan

Alexander George

Leonel R Nino

Matt Welch

Marx Thilo

Sabine Sch&ouml;niger Kieser

A method and circuit for controlling an output reference voltage generated by a reference voltage generator disposed on a memory device are provided. A signal for enabling a clocked standby mode of the memory device is received. If the signal indicates that the memory device is in the clocked standby mode, a first reference voltage is generated as the output reference voltage of the reference voltage generator using a first voltage. If the signal indicates that the memory device is not in the clocked standby mode, a second reference voltage is generated as the output reference voltage of the reference voltage generator using a second voltage.

Maintaining internal voltages of an integrated circuit in response to a clocked standby mode

A receiver for use in a device such as a memory device is provided. The receiver circuit is located on the same integrated circuit as a temperature sensor (or other sensor). A data receiver and strobe receiver are coupled to the temperature sensor. A flip-flop receives a data input from the data receiver and this data input is latched based upon the strobe receiver. In the preferred embodiment, the timing of these inputs is controlled, at least in part, by the temperature sensor output.

Circuit and method for adjusting threshold drift over temperature in a CMOS receiver

A memory device capable of performing a read operation includes: a memory array that stores data; and off-chip drivers that supply as an output of the memory device data retrieved from the memory array. At least one of the off-chip drivers includes: an enable circuit that generates an enable signal in response to a read enable signal received by the off-chip driver, wherein the enable circuit controls the timing of the enable signal in accordance with a timing signal supplied to the enable circuit; and a driver circuit that drives the data off the memory device in response to the enable signal.

Memory device having off-chip driver enable circuit and method for reducing delays during read operations

A method and apparatus for controlling a voltage generator of a memory device are provided. A temperature of the memory device is measured. If the measured temperature is outside a threshold temperature range, the memory device is allowed to be placed in a clocked standby mode (CSM), whereby the voltage generator is selectively enabled with a clock signal. If the measured temperature is within a threshold temperature range, the memory device is prevented from being placed in the clocked standby mode (CSM).

Disabling clocked standby mode based on device temperature

An integrated circuit includes a core memory array and a test mode compression circuit. The test mode compression circuit receives test mode data from the core memory array. A multiplexer receives read data from the core memory array and test mode data from the test mode compression circuit. The multiplexer receives a test mode compression signal and selectively transfers one of the read data and the test mode data dependent at least in part upon the test mode compression signal.

Method and apparatus for providing adjustable latency for test mode compression

A power down is implemented in a memory device capable of performing a read operation in which data and a data strobe signal are supplied as outputs. The power down techniques includes generating a first signal for preventing the data from being supplied as an output of the memory device, generating a second signal for causing the data strobe signal to remain in a predetermined state, and generating a third signal for preventing the data strobe signal in the predetermined state from being supplied as an output of the memory device.

Methods and apparatus for implementing a power down in a memory device

A random access memory includes a first circuit configured to receive a strobe signal and provide pulses in response to transitions in the strobe signal, and a second circuit configured to receive the strobe signal to latch data into the second circuit in response to the strobe signal, and to receive the pulses to re-latch the latched data into the second circuit after the transitions in the strobe signal. The first circuit includes an enable circuit configured to provide an enable signal and a buffer circuit configured to receive the strobe signal and the enable signal and provide the pulses in response to the enable signal and the strobe signal. The enable circuit is configured to receive the pulses from the buffer circuit and stop providing the enable signal to the buffer circuit in response to receiving the pulses.

Random access memory with post-amble data strobe signal noise rejection

A method of self-repair for a DRAM integrated circuit includes internally generating a bit pattern and writing the pattern to an array of memory cells within the integrated circuit. The DRAM integrated circuit reads from the array and internally compares the read data with the generated pattern to determine addresses for failed memory cells. The DRAM integrated circuit sets internal soft fuses that record the addresses of the failed memory cells and provide substitute memory cells for the failed memory cells from a redundant memory portion of the array. The self-repair process occurs each time the DRAM integrated circuit is powered up, thus permitting the integrated circuit to adapt to failures when installed in electronic devices and lessening the need for repair during manufacturing.

Method of self-repairing dynamic random access memory

A delay locked loop includes a delay unit with a controllable delay time. Switching elements are provided in order to tap off output signals from the delay elements of the delay unit. Two nodes connected to the switching elements are connected to a multiplexer configuration in order to activate in each case two of the switching elements that are connected to delay elements connected directly in succession. A phase interpolator generates an intermediate phase from the signals provided.

Delay locked loop

The present invention relates to a memory system including an external clock and a memory chip connected to the external clock. The external clock generates an operating signal at an operating frequency that controls at least one electrical component of the memory system. The memory chip includes a frequency detector that detects at least a range of frequency values for the operating frequency. Further, the frequency detector includes a reference frequency generator that generates a reference signal at a reference frequency.

On-die detection of the system operation frequency in a DRAM to adjust DRAM operations

A random access memory comprises a plurality of data pads and an array of memory cells comprising a first portion of memory cells and a second portion of memory cells. The random access memory comprises a first line configured to receive first data signals between the first portion of memory cells and the data pads and a second line configured to receive second data signals between the second portion of memory cells and the data pads. The first portion of memory cells is configured to be made inaccessible to eliminate the first data signals and a first number of the data pads and the second portion of memory cells is configured to be made inaccessible to eliminate the second data signals and a second number of the data pads.

Random access memory with optional inaccessible memory cells

The present invention relates to a method of operating a memory system comprising a memory chip. An operating signal is generated at an operating frequency. The operating frequency is applied to the memory chip to control one or more electrical components of the memory system. A reference signal is generated at a reference frequency within the memory chip and a range of values for the operating frequency is detected based on the reference signal and the operating signal.

Method for on-die detection of the system operation frequency in a DRAM to adjust DRAM operations

An output circuit (OUT) can be activated via an activation input (AKT), in the activated state starts an output process for data (D) to be read out, in synchronism with the first internal clock (CLKI), and outputs the data (D) with a specific phase shift (&#x394;TOUT) with respect to the first internal clock (CLKI), in synchronism with the external clock (CLKE), at a data connection (P). A counting unit (CT) starts a counting process for recording the number of successively following first levels of the first internal clock (CLKI) as soon as a second internal clock (CLKI), which is synchronized to the external clock (CLKE), for the first time assumes a first level while an output control signal (PAR) is at first level. It activates the output circuit (OUT) as soon as the number of successively following first levels of the first internal clock (CLKI) has reached a predetermined value.

Synchronous integrated memory

A method of protecting an integrated circuit that includes sensing a temperature of an integrated circuit, comparing the sensed temperature with a threshold temperature and controlling operation of the integrated circuit based on the comparing.

Use of an on-die temperature sensing scheme for thermal protection of DRAMS

A method of throttling the frequency with which an integrated circuit is accessed includes sensing the temperature of the integrated circuit die and converting the sensed temperature to a digital signal. The digital signal is stored in a register of the integrated circuit. The digital signal is read, and the frequency with which the integrated circuit is accessed is adjusted dependent at least in part upon the temperature of the die as indicated by the digital signal.

Growing community of inventors

Chapel Hill, NC, United States of America

Torsten Partsch