Robert Boschgmbh

Torsten Kramer

Hubert Benzel

Christoph Schelling

Simon Armbruster

Kathrin Knese

Stefan Pinter

Thomas Friedrich

Frieder Haag

Jens Frey

Arne Dannenberg

Matthias Illing

Joachim Fritz

Gregor Schuermann

Matthias Boehringer

Johannes Classen

Daniel Christoph Meisel

Florian Schoen

Christina Leinenbach

Daniel Meisel

Marcus Ahles

Karl-Heinz Kraft

Christian Lemier

Zhenyu Wu

Jens Schindele

Armin Grundmann

Simon Ambruster

A method for manufacturing a MEMS unit for a micromechanical pressure sensor. The method includes the steps: providing a MEMS wafer including a silicon substrate and a first cavity formed therein, under a sensor membrane; applying a layered protective element on the MEMS water; and exposing a sensor core from the back side, a second cavity being formed between the sensor core and the surface of the silicon substrate, and the second cavity being formed with the aid of an etching process which is carried out with the aid of etching parameters changed in a defined manner; and removing the layered protective element.

Method for manufacturing a MEMS unit for a micromechanical pressure sensor

A method for producing a micromechanical pressure sensor. The method includes: providing a MEMS wafer having a silicon substrate and a first cavity developed therein underneath a sensor diaphragm; providing a second wafer; bonding the MEMS wafer to the second wafer; and exposing a sensor core from the rear side; a second cavity being formed in the process between the sensor core and the surface of the silicon substrate, and the second cavity being developed with the aid of an etching process which is carried out using etching parameters that are modified in a defined manner.

Method for producing a stress-decoupled micromechanical pressure sensor

A method for manufacturing a semiconductor device in which a semiconductor substrate is provided, including a SOI-wafer having a carrier layer defining a rear side, a functional layer defining a front side. An insulation layer is situated between the carrier layer and functional layer. The functional layer includes a functional area having functional structures. The front side is masked, a first mask opening defines an interior area containing the functional area. The functional layer is removed by etching the front side. The rear side is masked, a second mask opening being configured, and a circumferential edge of the second mask opening is spaced outwardly relative to an outer circumferential edge of the interior area. The carrier layer and the insulation layer are removed at least in the area of the second-mask opening by etching to expose the interior area.

Method for manufacturing a semiconductor device and semiconductor device

A sensor element for thermal anemometry includes a semiconductor substrate and a thin-film diaphragm attached to the semiconductor substrate and having a front side and a rear side. A resistive heating element and a temperature-dependent resistor are attached to the front side of the thin-film diaphragm. In the area of the rear side of the thin-film diaphragm, the semiconductor substrate has a first recess. A silicon layer including a recess which merges with the first recess of the semiconductor substrate is located between the thin-film diaphragm and the semiconductor substrate.

Sensor element for thermal anemometry

A sensor unit including a first semiconductor component and a second semiconductor component, the first semiconductor component including a first substrate and a sensor structure. The second semiconductor component includes a second substrate, the first and second semiconductor components being connected to each other with the aid of a wafer connection, the sensor unit having a decoupling structure, which is configured in such a way that the sensor structure is decoupled thermally and/or mechanically from the second semiconductor component.

Sensor unit including a decoupling structure and manufacturing method therefor

Measures are provided which are used for stabilizing the substructure of the connecting areas of ASIC elements. These measures relate to ASIC elements including an ASIC substrate, into which electrical circuit functions are integrated, and including an ASIC layer structure on the ASIC substrate, which includes multiple wiring levels for the circuit functions, which are separated from one another by insulation layers and are interconnected via metallic plugs. At least one connecting area for placing wire bonds or for wafer bonding is implemented in at least one of the uppermost wiring levels. At least one chain of metallic plugs arranged vertically in a direct line is implemented in the ASIC layer structure below the connecting area, which extends from the uppermost wiring level up to the ASIC substrate or oxide trenches introduced therein.

ASIC element, in particular as a component of a vertically integrated hybrid component

A method for producing a component having at least one diaphragm formed in the upper surface of the component, which diaphragm spans a cavity, and having at least one access opening to the cavity from the back side of the component, at least one first diaphragm layer and the cavity being produced in a monolithic semiconductor substrate from the upper surface of the component, and the access opening being produced in a temporally limited etching step from the back side of the substrate. The access opening is placed in a region in which the substrate material comes up to the first diaphragm layer. The etching process for producing the access opening includes at least one anisotropic etching step and at least one isotropic etching step, in the anisotropic etching step, an etching channel from the back side of the substrate being produced, which terminates beneath the first diaphragm layer in the vicinity of the cavity, and at least the end region of this etching channel being expanded in the isotropic etching step until the etching channel is connected to the cavity.

Method for producing a component, and sensor element

A method for manufacturing a micromechanical diaphragm structure having access from the rear of the substrate includes: n-doping at least one contiguous lattice-type area of a p-doped silicon substrate surface; porously etching a substrate area beneath the n-doped lattice structure; producing a cavity in this substrate area beneath the n-doped lattice structure; growing a first monocrystalline silicon epitaxial layer on the n-doped lattice structure; at least one opening in the n-doped lattice structure being dimensioned in such a way that it is not closed by the growing first epitaxial layer but instead forms an access opening to the cavity; an oxide layer being created on the cavity wall; a rear access to the cavity being created, the oxide layer on the cavity wall acting as an etch stop layer; and the oxide layer being removed in the area of the cavity.

Method for manufacturing a micromechanical diaphragm structure having access from the rear of the substrate

A simple and economical method for manufacturing very thin capped MEMS components. In the method, a large number of MEMS units are produced on a component wafer. A capping wafer is then mounted on the component wafer, so that each MEMS unit is provided with a capping structure. Finally, the MEMS units capped in this way are separated to form MEMS components. A diaphragm layer is formed in a surface of the capping wafer by using a surface micromechanical method to produce at least one cavern underneath the diaphragm layer, support points being formed that connect the diaphragm layer to the substrate underneath the cavern. The capping wafer structured in this way is mounted on the component wafer in flip chip technology, so that the MEMS units of the component wafer are capped by the diaphragm layer. The support points are then cut through in order to remove the substrate.

Method for manufacturing capped MEMS components

A production method for chips, in which as many method steps as possible are carried out in the wafer composite, that is, in parallel for a plurality of chips disposed on a wafer. This is a method for producing a plurality of chips whose functionality is implemented on the basis of the surface layer of a substrate. In this method, the surface layer is patterned and at least one cavity is produced below the surface layer, so that the individual chip regions are connected to each other and/or to the rest of the substrate by suspension webs only, and/or so that the individual chip regions are connected to the substrate layer below the cavity via supporting elements in the region of the cavity. The suspension webs and/or supporting elements are cut when the chips are separated. The patterned and undercut surface layer of the substrate is embedded in a plastic mass before the chips are separated.

Method for producing a plurality of chips and a chip produced accordingly

A method for manufacturing chips (), in which at least one diaphragm () is produced in the surface layer of a semiconductor substrate () spanning a cavity (). The functionality of the chip () is then integrated into the diaphragm (). In order to separate the chip (), the diaphragm () is detached from the substrate composite. The method according to the present invention is characterized by metal plating of the back of the chip () in an electroplating process before the chip is separated.

Method for manufacturing chips

In a method for manufacturing a micromechanical chip, a sacrificial layer and an epitaxy layer are initially applied to a semiconductor substrate to produce a layer stack. An opening is subsequently introduced into the epitaxy layer from the front side of the layer stack. In order to electrically insulate the subsequent filling of the opening using a conductive contact layer from the material of the epitaxy layer, the walls of the opening are provided with an insulating layer. For removing the sacrificial layer and thus for producing the chip, separation trenches are subsequently etched through the epitaxy layer to the sacrificial layer also from the front side of the layer stack, which separation trenches also delimit the lateral extension of the chip.

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Wannweil, Germany

Torsten Kramer