Infineon Technologies Ag

Infineon Technologies Austria Ag

Qimonda Ag

Torsten Hinz

Martin Krueger

Marc Fahlenkamp

Thomas Duda

Jens Barrenscheen

Peter Gregorius

Andreas Jakobs

Marcus Schaemann

Martin Renner

Gerhard Risse

Josef Neulinger

Benaissa Zaryouh

Martin Feldtkeller

Anthony Sanders

Tommaso Bacigalupo

Christoph Braun

Armin Pitzer

Reinhard Mueller

Daniele Gardellini

Lajos Gaszi

A switched-mode power supply includes: a switching converter converts an input voltage into an output voltage in accordance with a switching signal, wherein the switching converter includes a transformer providing galvanic isolation between a primary side and a secondary side of the switching converter; and a wake-up circuit connected to the secondary side of the switching converter, the wake-up circuit coupled to the secondary side of the switching converter and operable to generate a feedback signal that indicates whether the output voltage is greater than or equal to a threshold value. A primary side regulator generates a control signal depending on a reference value and a measured value (V) representing the output voltage. Primary side logic generates the switching signal depending on the control signal. A tracking unit receives the feedback signal via a galvanically isolating component and adjusts the reference voltage based on the feedback signal.

Switched-mode power supply with wake-up circuitry

A power supply circuit is equipped with a converter circuit configured to convert an alternating current signal applied at an input of the power supply circuit into a direct current signal. A control circuit for the power supply circuit is configured to detect a phase of the alternating current signal and to control discharging of an internal capacitive element of the power supply circuit based on the detected phase of the alternating current signal.

Phase controlled discharging of internal capacitive element of power supply circuit

Techniques are described to adjust the time when a switch is turned on from the time of one voltage valley to the time of another voltage valley for controlling an average load current or average load voltage. In some examples, the adjustment is instantaneous, and in some examples, the adjustment is gradual. Both of these example techniques provide for high switching efficiency of the switch.

Valley to valley switching in quasi-resonant mode for driver

In accordance with an embodiment, a method of operating a switched-mode power converter includes defining at least one of a minimum switching frequency threshold and a maximum switching frequency threshold; detecting valleys occurring in a voltage over the switching element when the switching element is in an off-state; and either in a quasi-resonant mode, switching the switching element on when an nth consecutive valley occurs, n being an integer equal to or greater than one, so that the actual switching frequency is at least one of: below the maximum switching frequency threshold and above the minimum switching frequency threshold, or in a forced switching frequency mode, switching the switching element on so that the actual switching frequency is the maximum or the minimum switching frequency.

Switched-mode power conversion

In accordance with an embodiment, a method of operating a switched-mode power converter includes driving a switching element in successive drive cycles, in which the switching element is driven to switch on for an on-period and subsequently driven to switch off for an off-period; sampling a feedback signal two or more times during the drive cycles, where the feedback signal includes a signal representative of an operation parameter of the switched-mode power converter and noise. The method further includes filtering the sampled feedback signal to extract the signal representative of the operation parameter from the sampled feedback signal and controlling the switching element according to the filtered feedback signal.

Switched-mode power converter with sampled feedback signal

A method of cycle-by-cycle operation of a switched-mode power converter includes converting an input voltage at the primary side to an output voltage at the secondary side by switching a transistor connected to the primary side from an on-state to an off-state during the present cycle, detecting valleys in a voltage across the transistor in the off-state, determining which valley at which the transistor is to be switched from the off-state to the on-state in the next switching cycle, and determining a maximum peak current limit for the primary side above which the transistor is switched from the on-state to the off-state in the next switching cycle. The maximum peak current limit is determined as a function of the input voltage and the valley at which the transistor is to be switched from the off-state to the on-state in the next switching cycle. Forced valley switching techniques are also disclosed.

Peak power limitation and overpower protection for switched-mode power supplies

In accordance with an embodiment, a method includes driving an electronic switch in a switched-mode power converter in successive drive cycles, wherein driving the switch in each of the drive cycles comprises switching on the electronic for an on-period and subsequently switching off the electronic switch for an off-period. The method further includes establishing the on-period based on a comparison of an on-time signal with an off-threshold, calculating the off-threshold based on an output signal of the switched-mode power converter and a compensation offset, and calculating the compensation offset in one drive cycle based on an estimated delay time, wherein the estimated delay time is calculated based on a measured delay time and an estimated delay time of a previous drive cycle.

Power conversion with switch turn-off delay time compensation

An arbiter can be used for processing a plurality of asynchronous data signals. Each data signal is associated with a request signal and a respective acknowledge signal. The arbiter includes a latch array with an input coupled to receive the data signals and request signals and an output coupled to provide a data vector and a validity vector. The data vector includes values depending on the data signals and the validity vector includes values depending on the request signals when the latch array is in a transparent state. Logic circuitry is configured to trigger the latch array when any of the request signals becomes active, to activate a global request signal a delay time after the latch has been triggered, and to selectively activate the acknowledge signals for a channel or channels for which an active request signal has been latched.

Arbiter for asynchronous state machines

In accordance with an embodiment, a method includes driving an electronic switch in a switched-mode power converter in successive drive cycles, wherein driving the switch in each of the drive cycles comprises switching on the electronic for an on-period and subsequently switching off the electronic switch for an off-period, and measuring an operation parameter of the switched-mode power converter during the on-periods of the drive cycles, and storing the operation parameter measured in an on-period if a duration of the on-period met a predefined criteria. The method further includes forcing the on-period of a drive cycle to meet the predefined criteria if the operation parameter has not been stored for a predefined number of drive cycles, or for a pre-defined time duration.

Power conversion with external parameter detection

A power converter is described that includes a switch. The power converter may also include a controller that controls the switch. The controller may be configured to ascertain a first parameter. Additionally, the controller may be configured to ascertain a second parameter. The controller may dynamically modulate duty cycle of the switch based on the first parameter and the second parameter in addition and independent of the control loop.

Enhanced power factor correction

A circuit for operating loudspeakers includes a first, second, third and fourth loudspeaker circuit, having one input each for injecting a signal and one output each for connecting a loudspeaker input. The loudspeaker circuits are designed to amplify the injected signal and to provide the amplified signal at the outputs thereof. The loudspeaker circuits can, for example, be used for a 2.1 sound system. The three channels for a 2.1 sound system can be implemented by an amplifier circuit with four loudspeaker circuits, one loudspeaker circuit each being required for the two stereo channels left and right. A subwoofer channel can be driven differentially by two loudspeaker circuits. The stereo channels are, by contrast, only still connected to one loudspeaker circuit each, and so the stereo channels require at least one further common ground cable.

Method for driving loudspeakers

A method and a storage device for storing data in a flash memory drive are disclosed. In order to increase data throughput, the drive includes a cache memory including a tag memory and a plurality of flash devices coupled via a plurality of channels to the cache memory.

Method and apparatus for storing data in solid state memory

In an embodiment, an oversampled data converter includes a lowpass filter having a filter stage comprising a dynamic limiter, where the dynamic limiter having a limit set by an signal level at an input to the oversampled data converter. The oversampled data converter also includes a quantizing block comprising an input coupled to an output of the lowpass filter and an output coupled to an input of the lowpass filter.

Data converter circuit and method

An embodiment of the invention relates to a mass storage device including a nonvolatile memory device with a plurality of memory management blocks and an address translation table formed with pointers to locations of the memory management blocks. A volatile memory device is included with an address index table formed with pointers to the pointers to the locations of the memory management blocks. The address index table is stored in the nonvolatile memory upon loss of bias voltage. Changes to the address translation table are accumulated in the volatile memory and written to the address translation table when at least a minimum quantity of the changes has been accumulated. The changes to the logical block address translation table accumulated in the volatile memory are written to a page in the address translation table after prior data in the page has been updated, written to another page, and then erased.

Process and method for logical-to-physical address mapping using a volatile memory device in solid state disks

A memory arrangement comprises a first memory module and a second memory module. An item of information to be written to the memory arrangement is written with a first address both to the first memory module and to the second memory module. When reading, the item of information is read either from the first memory module by means of the first address or from the second memory module by means of a second address differing from the first address. Subsequently a check is made as to whether the item of information is defective. If this is the case, the item of information is read from the respective other memory module.

Growing community of inventors

Augsburg, Germany

Torsten Hinz