Omnivision Technologies, Inc.

Aptina Imaging Corporation

Micron Technology Incorporated

Semiconductor Components Industries, LLC

Tore Martinussen

Johannes Solhusvik

Robert Johansson

Trygve Willassen

Oyvind Janbu

Per Olaf Pahr

Jorgen Moholt

Sohrab Yaghmai

Sindre Mikkelsen

Jørgen Moholt

A CMOS image sensor comprises an array of pixels. A column of the pixel array is coupled to a readout column. The readout column is couple to a readout circuitry (RC) that reads out image data from the pixel array. The RC comprises a sampling switch which is coupled to a 1-column successive approximation register (SAR) analog-to-digital converter (ADC). The 1-column SAR ADC comprises a differential comparator, a local SAR control, and a digital-to-analog converter (DAC). The sampling switch is coupled between a readout column and a non-inverting input of the differential comparator. An image readout method reads one pixel with two conversions through the RC. The RC is operated by the local SAR control to set the DAC based on comparator output, and upon which a reset digital value is obtained and stored. An overall reduced algorithm calculation is achieved herein.

Digital CDS readout with 1.5 ADC conversions per pixel

A CMOS image sensor comprises an array of pixels. A column of the pixel array is coupled to a readout column. The readout column is couple to a readout circuitry (RC) that reads out image data from the pixel array. The RC comprises two sampling switches which are coupled to a 2-column successive approximation register (SAR) analog-to-digital converter (ADC). The 2-column SAR ADC comprises a differential comparator, a local SAR control, and two digital-to-analog converters (DACs). The two sampling switches are coupled between two readout columns and two inputs of the differential comparator, respectively. An image readout method reads two pixels with three conversions through the RC. The RC is operated by the local SAR control to set the two DACs based on comparator output, and upon which a reset digital value is obtained and stored. An overall reduced algorithm calculation is achieved herein.

An imager including a self test mode. The imager includes a pixel array for providing multiple pixel output signals via multiple columns; and a test switch for (a) receiving a test signal from a test generator and (b) disconnecting a pixel output signal from a column of the pixel array. The test switch provides the test signal to the column of the pixel array. The test signal includes a test voltage that replaces the pixel output signal. The test signal is digitized by an analog-to digital converter (ADC) and provided to a processor. The processor compares the digitized test signal to an expected pixel output signal. The processor also interpolates the output signal from a corresponding pixel using adjacent pixels, when the test switch disconnects the pixel output signal from the column of the pixel array.

Self test of image signal chain while running in streaming mode

A method of implementing extended range successive approximation analog-to-digital converter (ADC) starts with a readout circuitry acquiring an image data from a row in a color pixel array. ADC circuitry in the readout circuitry then generates an ADC pedestal for the row. Successive Approximation Register (SAR) included in ADC circuitry then stores ADC pedestal. SAR includes a plurality of bits and an additional bit that is a duplicate of one of the plurality of bits. ADC circuitry samples the image data from the row against ADC pedestal stored in SAR to obtain a sampled input data. ADC circuitry then converts the sampled input data from analog to digital to obtain an ADC output value. Other embodiments are described.

Method and system for implementing an extended range approximation analog-to-digital converter

An imager including a self test mode. The imager includes a pixel array for providing multiple pixel output signals via multiple columns; and a test switch for (a) receiving a test signal from a test generator and (b) disconnecting a pixel output signal from a column of the pixel array. The test switch provides the test signal to the column of the pixel array. The test signal includes a test voltage that replaces the pixel output signal. The test signal is digitized by an analog-to-digital converter (ADC) and provided to a processor. The processor compares the digitized test signal to an expected pixel output signal. The processor also interpolates the output signal from a corresponding pixel using adjacent pixels, when the test switch disconnects the pixel output signal from the column of the pixel array.

An imaging system may include an array of image pixels and verification circuitry. The verification circuitry may inject a test voltage into the pixel signal chain of a test pixel. The test voltage may be output on a column line associated with the column of pixels in which the test pixel is located. The test signal may be provided to a column ADC circuit for conversion from an analog test signal to a digital test signal. Verification circuitry may compare the digital output test signal with a predetermined reference signal to determine whether the imaging system is functioning properly (e.g., to determine whether column ADC circuits or other circuit elements in the pixel signal chain are functioning properly). If the output test signals do not match the expected output signals, the imaging system may be disabled and/or a warning signal may be presented to a user of the system.

Imaging systems with signal chain verification circuitry

A step-up converter includes an input coupled to receive a first voltage potential and an output coupled to output a second voltage potential higher than the first voltage potential. The step-up converter also includes an array of capacitance charge pumps. Each of the capacitance charge pumps in the array includes switches to be modulated to individually run each of the capacitance charge pumps by selectively connecting each of the capacitance charge pumps to the input and the output. The step-up converter further includes a control module coupled to the switches of each of the capacitance charge pumps and configured to modulate the switches at a substantially fixed frequency. The control module modulates the switches of selected capacitance charge pumps in the array in response to a current draw on the output. The step-up converter may be included in an image sensor.

Capacitance selectable charge pump

A novel image sensor includes a pixel array, a row control circuit, a test signal injection circuit, a sampling circuit, an image processing circuit, a comparison circuit, and a control circuit. In a particular embodiment, the test signal injection circuit injects test signals into the pixel array, the sampling circuit acquires pixel data from the pixel array, and the comparison circuit compares the pixel data with the test signals. If the pixel data does not correspond to the test signals, the comparison circuit outputs an error signal. Additional comparison circuits are provided to detect defects in the control circuitry of an image sensor.

System and method for sensor failure detection

Row-control signal monitoring system for an electronic imager includes signal processing circuitry coupled a pixel array of the electronic imager which receives at least one row control signal from the pixel array and provides an output signal corresponding to the selected row control signal. Monitoring circuitry compares the output signal to a target value to test the at least one row-control signal.

Imager row control-signal tester

Charge pumps and methods for regulating charge pumps. The charge pump includes a voltage booster circuit and a voltage regulator circuit. The voltage booster circuit includes first and second input terminals that respectively receive a regulation voltage and an input voltage. The voltage booster circuit generates an output voltage having a polarity that is different from the input voltage. The output voltage is adjusted by the regulation voltage and provided to an output terminal. The voltage regulator circuit is coupled between the first input terminal and the output terminal of the voltage booster circuit. The voltage regulator circuit shifts the output voltage to a level shifted voltage and generates the regulation voltage responsive to the level shifted voltage.

Comparator controlled charge pump for negative voltage booster

An imaging apparatus and a method using column processing circuits arranged in multiple rows for processing pixels in a pixel array.

Method and apparatus providing column parallel architecture for imagers

Apparatus and methods provide an operational transconductance amplifier (OTA) with one or more self-biased cascode current mirrors. Applicable topologies include a current-mirror OTA and a folded-cascode OTA. In one embodiment, the self-biasing cascode current mirror is an optional aspect of the folded-cascode OTA. The self-biasing can advantageous reduce the number of biasing circuits used, which can save chip area and cost. One embodiment includes an input differential pair of a current-mirror OTA.

Operational transconductance amplifier (OTA)

A reference current is generated by a current mirror circuit. An operational amplifier of a feedback circuit generates a control voltage for control of the feedback circuit transistor. The size of the feedback circuit transistor is trimmed, and the current through the feedback circuit transistor remains relatively constant via operation of the feedback circuit. The feedback circuit transistor is scaled in size relative to the size of current reference transistor(s) (e.g., current sources or sinks), which are tied to the same control voltage. The reference current of the current reference transistors thus varies with the size of the feedback circuit transistor. Further advantageously, transistors providing reference currents for resistor ladders can also be tied to the same control voltage, but scaled proportionally with changes in size to the feedback circuit transistor, thereby maintaining relatively constant voltage from taps of the resistor ladder, even when the feedback circuit transistor is trimmed.

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Strommen, Norway

Tore Martinussen