Telefonaktiebolaget Lm Ericsson (publ)

Marvellworld Trade Ltd.

Finisar Corporation

Optillion Operations Ab

Tord L Haulin

Heinz B Mader

Mats Olof Joakim Hedberg

Per M Segerback

Karl S Buhrgard

Tume Römer

In a network device, apparatus and methods perform precision time stamping. A time agent receives a master pace signal corresponding to a time representation based on a master real time clock in a master clock domain. A time accumulator accumulates time units one fill quantum at a time based on the master pace signal. The time accumulator decreases the accumulated time units by a leak quantum according to a local clock signal running at a higher frequency than the master pace signal. Correction logic periodically generates, at a granularity corresponding to the frequency of the local clock signal, an updated time representation in a target clock domain based on a residual number of time units in the time accumulator before depositing an additional fill quantum of time units in the time accumulator.

Methods and apparatus for precision time stamping

The present invention relates to service and maintenance solutions for programmable and/or reconfigurable modules (CM, . . . , CM), which are included in the nodes of a communications network (). The module (CM) contains a first digital storage unit (M), which holds information pertaining to the accomplishment of a primary function of the module. A secondary function of the module involves control of the primary function. The module has an optical bi-directional interface (I) towards the first digital storage unit. Data in the first digital storage unit may be read out (D) and may also be updated (D) by the portable software carrier unit via the optical bi-directional interface. Data read-out as well as data updating may be accomplished independently of the primary function. Preferably, an access module (A) controls the bi-directional interface in response to an authorization signal (SA) from an authorization unit ().

Service and maintenance solutions for programmable and/or reconfigurable modules included in communication network nodes

In a differential line receiver circuit having differential amplifier circuit where output rise and fall times are influenced by the ability of internal current sources to charge parasitic capacitances, a feedback circuit is provided to tune those current sources so as to deliver equal rise and fall time on both outputs. According to one embodiment a detector signal is derived from timing errors resulting from such rise and fall time discrepancies by means of a nested CMOS inverter arrangement coupled to an integrating element, and then used to control one or both of said current sources. It is further disclosed how deviations in the center voltage of the internal power supplies caused by the current source tuning can be allowed for by pre-processing of the signal at the input of the differential line receiver circuit by means of a differential signal transfer circuit which is able to impose a common mode signal on the input signal so as to match the center voltage of the differential amplifiers internal power supply.

Differential line receiver

A digital logic interface circuit makes use of a logic signal representative of a logic signaling level definition, to determine the logic swing amplitude of signals from a given source adopting the same logic signaling level definition. The digital logic interface circuit generates a threshold level from the logic swing amplitude thus determined, and compares digital logic input signals against the threshold level in order to discriminate different logic levels in the digital logic input signals. The comparison result is provided as digital interface output signals adopting a predetermined logic signaling level definition for use by subsequent system sections. Examples of such representative signals are the digital input logic signals themselves, clock signals or line encoded signals. Other examples can be mode control signals or NRZ signals.

Adaptive level binary logic

A differential signal transfer circuit to control the common mode level of a differential signal, comprising an input common mode level detection circuit, for detecting the common mode level of an incoming signal, two capacitors coupled between the first input and output and the second input and output respectively, and a control circuit adapted to control an output common mode voltage level at the output terminals by controlling the levels of charge on the two capacitors dependent on the common mode level of the incoming signal as detected by the input common mode detector.

Differential signal transfer circuit

A delay matched clock and data generator utilizes a re-timing element having the functionality of a two-input multiplexer, connected and operated such that the level on the output(s) is controlled from level control inputs, and the timing of transitions on the output(s) is controlled from timing control inputs. The level control inputs on the re-timing element correspond to the data input(s) on an equivalent multiplexer. The generator further has control inputs for stopping the clock low or stopping the clock high, and the generator may be operated for polarity independent clock gating or clock synthesis.

Generator for delay-matched clock and data signals

A fault tolerant queue system for selecting storing positions in a memory for performing write operations from an on-line maintained idle list of addresses to free storing positions in the memory and for calculating addresses for collecting data earlier stored in the memory. The storing positions are exposed to a testing procedure. The testing procedure is performed periodically on each storing position in idle cycles during operation of the system, and the result is used to maintain the idle list. The addresses selected for testing are released from system use as controlled by the system.

Fault tolerant queue system

A testing assembly, and an associated method, for testing an integrated circuit device. The testing assembly is capable of testing an integrated circuit device having a large number of input and output terminals formed of either single-ended terminals or differential terminals. Static testing, both functional and parametric, can be performed upon the integrated circuit device. Additionally, dynamic testing of the integrated circuit device, even integrated circuit devices operable at high frequencies, is possible through operation of the testing assembly. Test signals are applied by way of signal rails to the device undergoing testing. A test signal response indicator is coupled to observe responses to the test signals.

Assembly and method for testing integrated circuit devices

A bit synchronizer for the interpretation of a bit data stream received in a receiver when strobed by an isochronous or plesiochronous clock signal which lies in the receiver time domain is disclosed. This is achieved by alternate activation and deactivation of a first and a second phase aligner respectively, based on monitoring a delay controlled voltage of the active phase aligner. These phase aligners each utilizes differential delay lines which are comprised of differential delay elements, which in turn are comprised of pairs of inverting devices, where both devices of each pair have a controllable delay for positive edges and a pulse form restoring function for negative edges, alternatively a controllable delay for negative edges and a pulse form restoring function for positive edges. Because each DDE is constructed symmetrically, feedback from the outputs Q and Q on INV2 can be easily effected to the inputs FB and FB on INV1, and from the outputs Q and Q on INV1 in a delay element can be readily fed back to the inputs FB and FB respectively on INV2 in the preceding delay element. Because the feedback route quickly changes the ramp edge to full logic level as soon as the threshold voltage has been reached in the inverting device, the preceding stage is prepared for the restoring function that it will have for the next data edge, thereby avoiding interference effects.

Bit synchronizer

A fault tolerant queue system for buffering data in a packet switch with a common buffer memory for one or more output ports from the switch uses a number of pointers identifying storing positions in the buffer memory. Multiple copies of the same pointer are handled in a controlled way by using a multiple pointer list where the number of copies included in the system of respective pointers are recorded. A maintenance function checks that the number of copies of a pointer agrees with the value recorded in the multiple pointer list for the respective pointer. The maintenance function cyclically checks all pointers and appurtenant buffer positions, one at the time. This is preceded by an initiation procedure during which the pointer is taken out of operation by filtering out the pointer from the flow of pointers which from output queue lists for queueing pointers in queue to the output ports of the memory are returned to the idle list, until the queue system has been emptied of each copy of the pointer in question. Thereupon, the number of returned copies of the pointer in question is compared with the value in the multiple pointer list. The maintenance function can thereafter work in accordance with one or more operating modes for performing the cyclical control.

A signal processing arrangement processes an incoming bit position carrying signal and produces an outgoing bit position carrying signal. The arrangement comprises a signal processing unit for processing the incoming bit position carrying signal to produce an outgoing bit position carrying signal. The incoming bit position carrying signal is time-controlled in relation to a first clock signal. The outgoing bit position carrying signal is time-controlled in relation to the first clock signal. A second clock signal having the same frequency as the first clock signal is used for processing the incoming bit position carrying signal into a processed incoming bit position carrying signal within the signal processing unit. A synchronizing unit synchronizes processing for the signal processing unit by changing the time-relationship of clock pulses of the second clock signal to synchronize with the incoming bit position carrying signal. Buffer circuits store the processed incoming bit position carrying signal. The timing of the processed incoming bit position carrying signal can be changed to synchronize with clock pulses of the first clock signal before the processed incoming bit position carrying signal is output as the outgoing bit position carrying signal.

Signal processing arrangement

A device for monitoring supply voltage locally on integrated circuits after mounting on electronic component boards (11) includes at least one voltage monitor (31) as well as boundary scan means (36, 36', 37) for reading out the result of the monitoring. The monitor includes an extreme value detector (41), situated at the place on the circuit surface where voltage monitoring is desired and detecting the minimum absolute voltage between a local supply voltage lead and a local ground lead. The minimum value detector comprises one or two FET transistors at most.

Device for monitoring the supply voltage on integrated circuits

A method for avoiding latent errors in a logic network for majority selection of binary signals in a triplicated system. Errors which result from errors or faults in one of two or more parallel-connected transistors of one or more separate logic devices included in the logic network are avoided by repeatedly switching each of the separate logic devices in a manner such that transistors which were parallel-connected become series-connected, and vice versa. As a result, these devices will perform alternately logic operations which are the dual correspondence of one another, e.g. NAND- and NOR-operations with the aid of the same transistors (61-66) in both instances. Thus, in practice, majority selection will be performed alternately with two mutually different logic networks, which are the dual correspondence of each other.

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Uppsala, Sweden

Tord L Haulin