Intel Corporation

Other

Tor M Aamodt

Hong Wang

Per H Hammarlund

Perry H Wang

John P Shen

Steve Shih-wei Liao

Jared Warner Stark, Iv

Pedro Marcuello

Gerolf F Hoflehner

John Thomas Shen

Antonio Gonzalez

Antonio González

Shadi Assadikhomami

Ahmed Eltantawy

A system and method that detects that a group of threads has executed a spin-inducing branch in a single-instruction multithreaded processor and scheduling groups of threads based on the detection, marking the group as backed-off and deprioritizing the group for scheduling. When the group is scheduled a back-off counter is initialized and decremented each clock cycle. The group of threads is prevented from being scheduled if the spin-inducing branch is executed again before the counter reaches zero. A hardware system and method for labeling spin-inducing branches that determines that a profiled thread is in a spinning state and detects that a backward branch is executed while spinning. The detection is based on executions of a loop where the operand values for the exit condition don't change. A confidence level can be used that increases with each execution of a backward branch while in the spinning state.

Thread scheduling on SIMT architectures with busy-wait synchronization

An architecture for a Field Programmable Gate Array (FPGA) that better supports the designs of finite state machines (FSMs) generated by High-Level Synthesis (HLS) tools. The architecture is based on categorizing states of a FSM into branch free path states and independent states. A memory unit stores next state information for independent states and an accumulator unit computes next state information for branch free path states. A control unit selects the next state based on either the memory unit or the accumulator unit. An input sequence encoder encodes external inputs and current state values into encoded sequence signals that are input to the memory unit. Also disclosed is a state assignment algorithm that assigns state values to states of the FSM by first identifying branch free paths that terminate on the same state and then eliminating overlap between paths. States along the same branch free path are assigned sequential values.

State machine block for high-level synthesis

The latencies associated with retrieving instruction information for a main thread are decreased through the use of a simultaneous helper thread. The helper thread is a speculative prefetch thread to perform instruction prefetch and/or trace pre-build for the main thread.

Speculative multi-threading for instruction prefetch and/or trace pre-build

Embodiments of an apparatus, system and method enhance the efficiency of processor resource utilization during instruction prefetching via one or more speculative threads. Renamer logic and a map table are utilized to perform filtering of instructions in a speculative thread instruction stream. The map table includes a yes-a-thing bit to indicate whether the associated physical register's content reflects the value that would be computed by the main thread. A thread progress beacon table is utilized to track relative progress of a main thread and a speculative helper thread. Based upon information in the thread progress beacon table, the main thread may effect termination of a helper thread that is not likely to provide a performance benefit for the main thread.

Method and apparatus for efficient resource utilization for prescient instruction prefetch

Methods and an apparatus for generating a speculative helper thread for cache prefetch are disclosed. The disclosed techniques select spawn-target pairs based on profile data and a series of calculations. Helper threads are then generated to launch at the selected spawn points in order to prefetch software instructions (or data) for a single-threaded software application. The generated helper threads are then attached to the single-threaded software application to create a multi-threaded software application.

Methods and apparatus for generating speculative helper thread spawn-target points

Method and apparatus for efficient utilization for prescient instruction prefetch

Growing community of inventors

Toronto, Canada

Tor M Aamodt