Nec Corporation

Tooru Yasuda

Naoki Mukawa

Mitsuo Nishiwaki

Shuzo Tsugane

Tooru Amano

Sakae Okubo

A television conference system includes, in a transmitting side, a plurality of TV cameras assigned with camera ID codes, and in a receiving side, a plurality of TV monitors assigned with monitor ID codes and frame memories for storing inputs to the TV monitors. In the transmitting side, a moving picture signal output from a TV camera selected by a camera ID number is encoded, and the encoded moving picture signal together with a monitor ID code of a TV monitor designated to display an output from the selected TV camera are transmitted to the receiving side. In the receiving side, writing is performed in a frame memory corresponding to the TV monitor designated by the monitor ID signal to display a moving picture on the TV monitor, writing in each of the frame memories corresponding to the other TV monitors is inhibited and the last frame of the latest moving picture displayed thereon is displayed as a still picture, and selection of the TV camera and designation of the TV monitor are arbitrarily performed.

Television conference system including many television monitors and

A system for decoding a coded inter-frame prediction signal comprises a separating circuit (4) for separating the coded signal into a coded prediction error signal (b.sub.k) and a remainder (r.sub.k). A decoding circuit (5, 6, 7) generates a decoded prediction error signal x.sub.k. A first delay circuit (8) provides the decoded signal with a first delay to produce a first delayed signal. An error detecting circuit (11, 13) detects errors in the decoded signal (x.sub.k) and generates an error detection signal which has a high or low level, depending on whether an error has been detected for a given frame. A second delay circuit (10) provides the output of the decoding system with a second delay to produce a second delayed signal. A selecting circuit (14, 9) receives the error detection signal and the first and second delayed signals and selects one of the latter to produce the output of the decoding system.

Inter-frame decoding system with frame memories for uninterrupted clear

In a digital data communication network comprising digital data transmitting and receiving devices (111, 122) and first and second digital communication paths (16, 17) connected to each other and to the transmitting and the receiving devices, respectively, a stuffing circuit (23) is controlled by a control signal producing circuit (24) so as to stuff and not to stuff an input bit sequence when at least one of the first and the second digital communication paths has a restricted transmission characteristic and when both of the communication paths have an unrestricted transmission characteristic. Preferably, necessity and unnecessity of stuffing should be detected for a leading and a trailing part of each block with a shorter interval of time than for other parts of the block. More preferably, some of binary one bits placed at the beginnings of the respective blocks are used as a part of a multiframe synchronization pattern for a signal transmitted through the communication paths.

Digital data transmitting device for communication paths of restricted

According to the present invention, an encoding system has an interframe encoder for interframe encoding of video signals to supply predictive encoded signals, and a scan converter for converting the predictive encoded signals into predictive encoded signals of a predetermined block structure. A code converter converts effective picture elements in the block-structured predictive encoded signals into variable length codes and ineffective picture elements therein into run length codes. A buffer memory not only stores the code-converted codes but also calculates their occupancy quantity. The present encoding system is further provided with a buffer simulator for calculating, on the basis of the predictive encoded signals and the code-converted signals, the quantity of information stored in the scan converter, an adder for adding simulated information and the buffer occupancy quantity, and a control circuit for controlling generation of interframe encoding information on the basis of the added signals.

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Tokyo, Japan

Tooru Yasuda