Fujitsu Corporation

Tooru Shinohara

Masahito Iwatsubo

Toshifumi Hatagami

A delay circuit which compensates for a variable phase output of an index signal by delaying the read out index signal. The delay time of the delay circuit depends on the cylinder on which a read/write head is located, and is chosen so that the delayed index signals are generated at an essentially constant phase angle with respect to a reference angular position. The delay circuit may include a counter which is pre-loaded with an address of the cylinder on which the head is located, and which counts number of clock pulses input to the counter. Overflowing of the counter generates the compensated index signal. Thus, synchronous operation of plural disk apparatus is accomplished, when the head seeks a new cylinder.

Growing community of inventors

Kawasaki, Japan

Tooru Shinohara