Nxp B.v.

Tony Vanhoucke

Hans Mertens

Evelyne Gridelet

Johannes Josephus Theodorus Marinus Donkers

Petrus Hubertus Cornelis Magnee

Viet Thanh Dinh

Blandine Duriez

Jan Willem Slotboom

Anco Heringa

Mahmoud Shehab Mohammad Al-Sa'di

Dirk Klaassen

Philippe Meunier-Beillard

Gian Hoogzaad

Mark Pieter Van Der Heijden

Godefridus A M Hurkx

Johannes Donkers

Gerben Willem De Jong

Rob Van Dalen

Jozef Reinerus Maria Bergervoet

Gerhard Koops

Viet Nguyen

Michiel Jos Van Duuren

Sebastien Nuttinck

Dusan Golubovic

Joost Melai

Ihor Brunets

Ivan Mitkov Zahariev

Johannes Theodorus Marinus Donkers

Godefridus Hurkx

Ivan Matkov Zahariev

Ponky Ivo

Godefridus Antonius Maria Hurxk

Johannes Josephus Theodorus Martinus Donkers

Evelyne Marie Josephe Fabienne Gridelet

An embodiment of a semiconductor device may include a semiconductor substrate, a first semiconductor region comprising a first material with a first polarity formed within the semiconductor substrate and a second semiconductor region comprising the first material with a second polarity formed within the semiconductor substrate and coupled to the first semiconductor region. In an embodiment, a semiconductor device may also include a first electrode coupled to the first semiconductor region, a second electrode coupled to the second semiconductor region, and a depletion region formed between the first semiconductor region and the second semiconductor region. The depletion region may include a mixed crystal region that includes a mixed crystal alloy of the first material and a second material, wherein the mixed crystal region has a lower bandgap energy than a bandgap energy of the first material.

Semiconductor devices with a mixed crystal region

An embodiment of a semiconductor device includes a first semiconductor region formed within a semiconductor substrate, a second semiconductor region formed within the semiconductor substrate, a first electrode coupled to the first semiconductor region, a second electrode coupled to the second semiconductor region and proximate the first electrode, wherein the second electrode is encircled by the first electrode. A third electrode may be coupled to the first electrode and the second semiconductor region. A fourth electrode may be coupled to the first semiconductor region and proximate the third electrode, wherein the fourth electrode may be coupled to the second electrode, and wherein the third electrode includes a shared portion of the first electrode.

Semiconductor device with an encircled electrode

A semiconductor switch device and a method of making the same. The device includes a semiconductor substrate having a major surface. The device also includes a first semiconductor region located in the substrate beneath the major surface. The device includes an elongate gate located on the major surface. The device also includes a source region and a drain region located in the first semiconductor region adjacent respective first and second elongate edges of the gate. The device also includes electrical contacts for the source and drain regions. The contacts include at least two contacts located on either the source region or the drain region, which are spaced apart along a direction substantially parallel the elongate edges of the gate. The device further includes an isolation region located between the at least two contacts. The isolation region extends through the source/drain region from the major surface to the first semiconductor region.

Semiconductor switch device and method having at least two contacts located on either the source region or the drain region

A flip chip circuit comprising: a semiconductor substrate; a power amplifier provided on the semiconductor substrate; and a metal pad configured to receive an electrically conductive bump for connecting the flip chip to external circuitry. At least a portion of the power amplifier is positioned directly between the metal pad and the semiconductor substrate.

Flip chip circuit

A method of identifying a component by a response to a challenge is disclosed, the component comprising an array of bipolar transistors connectable in parallel so as to have a common collector contact, a common emitter contact and a common base contact, the challenge comprising a value representative of a total collector current value, the method comprising: receiving the challenge; supplying the total collector current to the common collector contact; detecting instability in each of a group of the transistors; and determining the response in dependence on the group. A circuit configured to operate such a method is also disclosed.

PUF method using and circuit having an array of bipolar transistors

A Doherty amplifier circuit comprising: a splitter having: a splitter-input-terminal for receiving an input signal; a main-splitter-output-terminal; and a peaking-splitter-output-terminal; a main-power-amplifier having a main-power-input-terminal and a main-power-output-terminal, wherein; the main-power-input-terminal is connected to the main-splitter-output-terminal; and the main-power-output-terminal is configured to provide a main-power-amplifier-output-signal; a peaking-power-amplifier having a peaking-power-input-terminal and a peaking-power-output-terminal, wherein: the peaking-power-input-terminal is connected to the peaking-splitter-output-terminal; and the peaking-power-output-terminal is configured to provide a peaking-power-amplifier-output-signal. The splitter, the main-power-amplifier and the peaking-power-amplifier are provided by means of an integrated circuit.

Doherty amplifier circuits

Disclosed is a transistor having a first region of a first conductivity type for injecting charge carriers into the transistor and a laterally extended second region of the first conductivity type having a portion including a contact terminal for draining said charge carriers from the transistor, wherein the first region is separated from the second region by an intermediate region of a second conductivity type defining a first p-n junction with the first region and a second p-n junction with the second region, wherein the laterally extended region separates the portion from the second p-n junction, and wherein the transistor further comprises a substrate having a doped region of the second conductivity type, said doped region being in contact with and extending along the laterally extended second region and a further contact terminal connected to the doped region for draining minority charge carriers from the laterally extended second region. An amplifier circuit and IC including such transistors are also disclosed.

Transistor amplifier circuit and integrated circuit

The disclosure relates to bipolar transistor devices and a method of fabricating the same. The device comprises a field plate, in an isolation region adjacent to a base-collector junction of said active region. The isolation region comprises a gate terminal arranged to be biased independently of a collector, base or emitter terminal of said transistor.

Bipolar transistor device and method of fabrication

A semiconductor device comprising a bipolar transistor and a method of making the same. The bipolar transistor includes a collector having a laterally extending drift region. The bipolar transistor also includes a base located above the collector. The bipolar transistor further includes an emitter located above the base. The bipolar transistor also includes a reduced surface field (RESURF) gate located above an upper surface of the laterally extending drift region for shaping an electric field within the collector. The bipolar transistor further includes a gap located between the reduced surface field gate and an extrinsic region of the base of the device, for electrically isolating the reduced surface field gate from the base. A lateral dimension Lof the gap is in the range 0.1 &#x3bc;m&#x2266;L&#x2266;1.0 &#x3bc;m.

Semiconductor device comprising a bipolar transistor

A semiconductor device comprising a bipolar transistor and a method of making the same. A power amplifier including a bipolar transistor. The bipolar transistor includes a collector including a laterally extending drift region. The also includes a base located above the collector. The bipolar transistor further includes an emitter located above the base. The bipolar transistor also includes a doped region having a conductivity type that is different to that of the collector. The doped region extends laterally beneath the collector to form a junction at a region of contact between the doped region and the collector. The doped region has a non-uniform lateral doping profile. A doping level of the doped region is highest in a part of the doped region closest to a collector-base junction of the bipolar transistor.

Bipolar transistor

A circuit, comprising a semiconductor device with one or more field gate terminals for controlling the electric field in a drift region of the semiconductor device; and a feedback circuit configured to dynamically control a bias voltage or voltages applied to the field gate terminal or terminals, with different control voltages used for different semiconductor device characteristics in real-time in response to a time-varying signal at a further node in the circuit.

Semiconductor device and circuit with dynamic control of electric field

Disclosed is a method of manufacturing a vertical bipolar transistor in a CMOS process, comprising implanting an impurity of a first type into a the substrate () to form a buried region () therein; forming a halo implant () using an impurity of a second type and a shallow implant () using an impurity of the first type, said halo implant enveloping the shallow implant in the substrate and being located over said buried region (); forming, adjacent to the halo implant (), a further implant () using an impurity of the second type for providing a conductive connection to the halo implant; and providing respective connections () to the further implant (), the shallow implant () and the buried region () allowing the shallow implant, halo implant and buried region to be respectively operable as emitter, base and collector of the vertical bipolar transistor. Hence, an IC may be provided that comprises vertical bipolar transistors manufactured using CMOS processing steps only.

IC and IC manufacturing method

Disclosed is a method of manufacturing an integrated circuit comprising a bipolar transistor, the method comprising providing a substrate () comprising a pair of first isolation regions () separated from each other by an active region () comprising a collector impurity said bipolar transistor; forming a base layer stack (') over said substrate; forming a further stack of a migration layer () having a first migration temperature and an etch stop layer () over said base layer stack (); forming a base contact layer () having a second migration temperature over the further stack, the second migration temperature being higher than the first migration temperature; etching an emitter window () in the base contact layer over the active region, said etching step terminating at the etch stop layer; at least partially removing the etch stop layer, thereby forming cavities () extending from the emitter window in between the base contact layer and the redistribution layer; and exposing the resultant structure to the first migration temperature in a hydrogen atmosphere, thereby filling the cavities with the migration layer material. An IC comprising such a bipolar transistor is also disclosed.

Method of manufacturing IC comprising a bipolar transistor and IC

Methods and systems for processing a silicon wafer are disclosed. A method includes providing a flash memory region in the silicon wafer and providing a bipolar transistor with a polysilicon external base in the silicon wafer. The flash memory region and the bipolar transistor are formed by depositing a single polysilicon layer common to both the flash memory region and the bipolar transistor.

Method of processing a silicon wafer and a silicon integrated circuit

A semiconductor device and a method of making the same. The device includes a semiconductor substrate. The device also includes a bipolar transistor on the semiconductor substrate. The bipolar transistor includes an emitter. The bipolar transistor also includes a base located above the emitter. The bipolar transistor further includes a laterally extending collector located above the base. The collector includes a portion that extends past an edge of the base.

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Bierbeek, Belgium

Tony Vanhoucke