Motorola Corporation

Tony Tong-Khay Cheng

John P Dunn

Anthony M Reipold

Jose A Lyon

James C Nash

Theo C Freund

Joseph M Harris, Ii

Eric Hoang

A method and apparatus for allowing the soft defect detection testing (SDDT) of an memory array (106) of a data processor (100) begins by providing a control value to a memory controller (111). The control value determines whether a switching circuit (104) will apply a VDD power supply voltage from a VDD terminal (132) or a Vstby power supply voltage from a Vstby terminal (130) to a selected portion of the memory array (106). When in an SDDT test mode, the selected portion of the memory array (106) is supplied by the Vstby terminal (130). While being supplied by the Vstby terminal (130), the selected portion of the memory array (106) is SDDT tested by coupling a current detection device to the pin (130) and measuring a current I drawn by the selected portion of the memory array (106).

Method and apparatus for testing on-chip memory on a microcontroller

A method and apparatus for viewing the contents of an internal bus (112) external to a integrated circuit (100) begins by providing a integrated circuit (100) which has the internal bus (112). Internal bus is not itself accessible to the external terminals of the integrated circuit (100). When an access on the bus (112) needs to be viewed external to the integrated circuit (100), a control section (120) forces the signals/access on the bus (112) to a second slower bus (114) within the integrated circuit (100). The second bus is coupled to circuitry (160) which is coupled to external terminals so that the external terminals can be used to inspect the contents of the bus (112) by using the bus (114) as an intermediary.

Method and apparatus for external viewing of an internal bus

A data processing system (10) implements state machine (82) and register logic (80) such that no external control or data is required during execution of a dual scan path test operation. Prior to execution of the dual scan path test operation, a user of data processing system (10) initializes a system with a plurality of values which will be used during execution of the dual scan path test operation. After initialization, data processing system (10) executes the dual scan path test operation automatically and requires no additional information from the user.

Method and apparatus for performing dual scan path testing of an array

Growing community of inventors

Austin, TX, United States of America

Tony Tong-Khay Cheng