Texas Instruments Corporation

Other

Tony Thanh Phan

Martin B Mollat

Philip Leland Hower

John Lin

William C Loftin

Ming-Yeh Chuang

Richard B Irwin

Farris D Malone

Kyle Mitchell Flessner

Patrick J Jones

Jennifer S Dumin

Fredric D Bailey

Hong-Ryong Kim

Bradley T Moore

Eric W Beach

Mohamed el-Hamdi

Milind V Khandekar

Daniel Tsai

Luther Hendrix

Connie Wang

Arthur Pan

Michelle R Keramidas

Karen Elizabeth Burks

Formation of an electrostatic discharge (ESD) protection device having a desired breakdown voltage (BV) is disclosed. The breakdown voltage (BV) of the device can be set, at least in part, by varying the degree to which a surface junction between two doped areas is covered. This junction can be covered in one embodiment by a dielectric material and/or a semiconductor material. Moreover, a variable breakdown voltage can be established by concurrently forming, in a single process flow, multiple diodes that have different breakdown voltages, where the diodes are also formed concurrently with circuitry that is to be protected. To generate the variable or different breakdown voltages, respective edges of isolation regions can be extended to cover more of the surface junctions of different diodes. In this manner, a first diode can have a first breakdown voltage (BV), a second diode can have a second breakdown voltage (BV), a third diode can have a third breakdown voltage (BV), etc. This can provide substantial efficiency and cost savings where there may be varying ESD requirements.

High-voltage variable breakdown voltage (BV) diode for electrostatic discharge (ESD) applications

An embodiment of the invention is a Schottky diodehaving a semiconductor substrate, a first metal, a barrier layer, and second metal. Another embodiment of the invention is a method of manufacturing a Schottky diodethat includes providing a semiconductor substrate, forming a barrier layerover the semiconductor substrate, forming a first metal layerover the semiconductor substrate, annealing the semiconductor substrateto form areasof reacted first metal and areasof un-reacted first metal, and removing selected areasof the un-reacted first metal. The method further includes forming a second metal layerover the semiconductor substrateand annealing the semiconductor substrateto form areasof reacted second metal and areasof un-reacted second metal.

Method of manufacturing a dual metal Schottky diode

A method for manufacturing a semiconductor device that method comprises forming a thin film resistor by a process that includes depositing a resistive material layer on a semiconductor substrate. The process also includes depositing an insulating layer on the resistive material layer, and performing a first dry etch process on the insulating layer to form an insulative body. The process further includes performing a second dry etch process on the resistive material layer to form a resistive body. The resistive body and the insulative body have substantially identical perimeters.

Method to manufacture a thin film resistor

The present invention provides an integrated circuit and a method of manufacture therefore therefor. The integrated circuit (), in one embodiment without limitation, includes a dielectric layer () located over a wafer substrate (), and a semiconductor substrate () located over the dielectric layer (), the semiconductor substrate () having one or more transistor devices () located therein or thereon. The integrated circuit () may further include an interconnect () extending entirely through the semiconductor substrate () and the dielectric layer (), thereby electrically contacting the wafer substrate ().

Integrated circuit having a top side wafer contact and a method of manufacture therefor

The present invention provides method of manufacturing a metal-insulator-metal capacitor (). A method of manufacturing includes depositing a first refractory metal layer () over a semiconductor substrate (). The first refractory metal layer () over a capacitor region () of the semiconductor substrate () is removed and a second refractory metal () is deposited over the capacitor region (). Other aspects of the present invention include a metal-insulator-metal capacitor () and a method of manufacturing an integrated circuit ().

Method of manufacturing a metal-insulator-metal capacitor

The present invention provides a method for analyzing critical defects in analog integrated circuits. The method for analyzing critical defects, among other possible steps, may include fault testing a power field effect transistor () portion of an analog integrated circuit () to obtain electrical failure data. The method may further include performing an in-line optical inspection of the analog integrated circuit () to obtain physical defect data, and correlating the electrical failure data and physical defect data to analyze critical defects.

Methods for analyzing critical defects in analog integrated circuits

The present invention provides an integrated circuit and a method of manufacture therefore. The integrated circuit (), in one embodiment without limitation, includes a dielectric layer () located over a wafer substrate (), and a semiconductor substrate () located over the dielectric layer (), the semiconductor substrate () having one or more transistor devices () located therein or thereon. The integrated circuit () may further include an interconnect () extending entirely through the semiconductor substrate () and the dielectric layer (), thereby electrically contacting the wafer substrate ().

The present invention provides an integrated circuit and a method of manufacture therefor. The integrated circuit (), in one embodiment without limitation, includes a dielectric layer () located over a wafer substrate (), and a semiconductor substrate () located over the dielectric layer (), the semiconductor substrate () having one or more transistor devices () located therein or thereon. The integrated circuit () may further include an interconnect () extending entirely through the semiconductor substrate () and the dielectric layer (), thereby electrically contacting the wafer substrate (), and one or more isolation structures () extending entirely through the semiconductor substrate () to the dielectric layer ().

Integrated circuit having a transistor level top side wafer contact and a method of manufacture therefor

A method of fabricating a thin film resistor (). The resistor material (), e.g., NiCr, is deposited. A hard mask material (), e.g., TiW, may be deposited over the resistor material (). The resistor material () and hard mask material () are patterned and sputter etched to form the resistor body. For example, a sputter etch chemistry comprising BCl, Cl, and Ar may be used to etch the resistor material.

Method to produce thin film resistor using dry etch

The present invention provides a method for manufacturing a metal-insulator-metal (MIM) capacitor, a method for manufacturing an integrated circuit having a metal-insulator-metal (MIM) capacitor, and an integrated circuit having a metal-insulator-metal (MIM) capacitor. The method for manufacturing the metal-insulator-metal (MIM) capacitor, among other steps and without limitation, includes providing a material layer () over a substrate (), and forming a refractory metal layer () having a thickness (t) over the substrate (), at least a portion of the refractory metal layer () extending over the material layer (). The method further includes reducing the thickness (t) of the portion of the refractory metal layer () extending over the material layer (), thereby forming a thinned refractory metal layer (), and reacting the thinned refractory metal layer () with at least a portion of the material layer () to form an electrode () for use in a capacitor.

Method of manufacturing a metal-insulator-metal capacitor using an etchback process

Dual metal Schottky diode

Various methods are provided of forming capacitor electrodes for integrated circuit memory cells in which out-diffusion of dopant from doped silicon layers is controlled by deposition of barrier layers, such as layers of undoped silicon and/or oxide. In one aspect, a method of forming hemispherical grain silicon on a substrate is provided that includes forming a first doped silicon layer on the substrate and a first barrier layer on the doped silicon layer. A hemispherical grain polysilicon source layer is formed on the first barrier layer and a hemispherical grain silicon layer on the hemispherical grain polysilicon source layer. By controlling out-diffusion of dopant, HSG grain size, density and uniformity, as well as DRAM memory cell capacitance, may be enhanced, while at the same time maintaining reactor throughput.

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Flower Mound, TX, United States of America

Tony Thanh Phan