Standard Microsystems Corporation

Oasis Design, Inc.

Microchip Technology Inc.

Smsc Holdings Sarl

Tony Susanto

David J Knapp

Edmund Mark Schneider

Wesley Ladd Mokry

David S Trager

Maarten Kuijk

Larry L Harris

Zhonghong Shen

Tihsiang Hsu

An adaptive mode has been added in a common mode (CM) dimmer circuit to increase output current capability only when needed. Without having an adaptive mode in the CM dimmer, the output current drivers must operate with large quiescent current to handle a bulk current injection (BCI) event. Therefore, a CM dimmer without the adaptive mode will consume a significant amount of power even when there is no BCI event occurring. With the adaptive mode, the CM dimmer can be used effectively to suppress the BCI event, e.g., in a transformer-less physical layer (PHY) connection, while consuming minimal power during normal circuit operation.

Adaptive common mode dimmer

An optical receiver, within a first device, may receive first configuration information from an optical transmitter, also within the first device. While receiving the first configuration information, the optical receiver may operate according to a clock. Later, the optical receiver may receive optical data from a second device according to the first configuration. While receiving the optical data from the second device, the optical receiver does not operate according to the clock, wherein the optical receiver not operating according to the clock allows the optical receiver to receive the optical data with greater sensitivity.

Communicating between an optical receiver and an optical transmitter using a serial bus

A communication network is provided for interconnecting a network of digital systems, such as multimedia devices. Each node of the communication network may include a receiver and a transmitter. The receiver and transmitter of each node can be an optical receiver and transmitter. The optical receiver is preferably powered by two power supply pins, each providing different supply amounts. An activity detector within the receiver can be powered from a first supply amount, and the signal path of the optical receiver can be supplied from a second supply amount greater than the first supply amount. The first supply amount is provided at all times, and the second supply amount is only provided if activity is detected. A voltage regulator which provides the first supply amount can be beneficially embodied on the same integrated circuit as a network interface to reduce the manufacturing cost of the network. By powering the activity detector separate from the signal path, power down and power up (normal) operating states are envisioned for reducing power consumption and increasing longevity of the optical receiver and transmitter.

Transmission network having an optical receiver that utilizes dual power pins and a single status pin to lower power consumption, lower manufacturing cost, and increase transmission efficiency

An apparatus is provided for automatically and dynamically adjusting a frequency division factor of a clock divider situated in the feedback loop of a phase-locked loop (PLL). The frequency division factor is modified based on changes in the input signal frequency forwarded to the PLL. If the input signal frequency increases, the decision circuit coupled to the input of the voltage controlled oscillator records that change as an encoded digital signal. That signal will accordingly modify the current frequency division factor dependent on current division factor as well as the current input signal frequency. The decision circuit can be modeled as an A/D converter, and the control unit placed between the decision circuit and the clock divider can be modeled as a state diagram. Each state of the state diagram is indicative of a frequency division factor, or a change in that division factor, wherein the coded digital signal indicates possible change from one state to another. By modifying the frequency division factor, the PLL can dynamically lock upon a changed input signal frequency without varying the clocking signal output from the PLL. Thus, the PLL can accommodate various input signal frequencies yet maintain a relatively fixed clocking signal to be forwarded as a timing reference to a digital processor.

Phase-locked loop which can automatically adjust to and lock upon a

A circuit is provided for controlling or regulating a phase-locked loop (PLL) output during times when the PLL is unlocked. Noise or corruption on the input signal of the PLL may cause the PLL output frequency to suddenly rise to match the input signal frequency. In many instances, the noise or corruption cannot be filtered by the low pass filter within the PLL. A detection circuit is coupled to receive the input signal, and discern times in which non-filterable noise occurs. The detection circuit may include a decoder which decodes, e.g., error correction coding within the input signal data stream to indicate possible instances in which the PLL will unlock. Once the detection circuit indicates an unlock condition and forwards an unlock selection signal to a multiplexer, the multiplexer chooses a frequency divided clocking signal rather than the PLL output clocking signal. The frequency divided clocking signal transitions at a rate acceptable to a digital processor, while the PLL output clocking signal during an unlock state is not acceptable. Thus, the digital processor can maintain its operating state during times when the PLL clocking signal exceeds the processor maximum operation frequency.

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Austin, TX, United States of America

Tony Susanto