Altera Corporation

Lam Research Corporation

Tony San

Philippe Molson

John C Valcore, Jr

Andrew Fong

Jinyan Zhang

Seonkyung Lee

Jeffrey Fox

Bostjan Pust

Maria D'Souza

A system and a method for increasing a rate of transfer of data between a radio frequency (RF) generator and a host computer system is described. The rate of transfer of data is increased by implementing dedicated physical layers associated with the RF generator and the host computer system and a dedicated physical communication medium between the RF generator and the host computer system. Moreover, a dual push operation is used between the RF generator and the host computer system. There is no request for data sent from the RF generator to the host computer system or from the host computer system to the RF generator.

Dual push between a host computer system and an RF generator

A system and method monitoring a plasma with an optical sensor to determine the operations of a pulsed RF signal for plasma processing including a plasma chamber with an optical sensor directed toward a plasma region. An RF generator coupled to the plasma chamber through a match circuit. An RF timing system coupled to the RF generator. A system controller is coupled to the plasma chamber, the RF generator, the optical sensor, the RF timing system and the match circuit. The system controller includes a central processing unit, a memory system, a set of RF generator settings and an optical pulsed plasma analyzer coupled to the optical sensor and being capable to determine a timing of a change in state of an optical emission received in the optical sensor and/or a set of amplitude statistics corresponding to an amplitude of the optical emission received in the optical sensor.

System, method and apparatus for using optical data to monitor RF generator operations

Systems and methods for synchronizing execution of recipe sets are described. One of the methods includes sending by a command controller to a master controller a recipe set and sending by the master controller the recipe set for execution by a sub-system controller of a plasma system. The operation of sending the recipe set from the master controller to the sub-controller is performed during a first clock cycle of a clock signal. The method includes generating by the command controller a recipe event signal and sending by the command controller to the sub-system controller the recipe event signal indicating a time of execution of the recipe set by the sub-system controller. The time of execution occurs during a second clock cycle that follows the first clock cycle. The second cycle is of the clock signal.

Systems and methods for synchronizing execution of recipe sets

A signal decimating system decimates an initial data signal having an initial data rate R to a final data signal having a final data rate R&#x2033; in two stages, using a base decimation factor N and a decimation multiplier factor P. In the first stage, N FIR filters having coefficients corresponding to the final data rate R&#x2033; condition the initial data signal using the final data rate coefficients and thereafter decimate the initial data signal, as conditioned, by a base decimation factor of N to generate an intermediate data signal having an intermediate data rate R', where In the second stage, a sub-sampling unit includes a switch that sub-samples the intermediate data signal at a sub-sampling rate P to generate a final data signal having a final data rate R&#x2033;, where 

Dynamically re-configurable signal decimation system using a finite impulse response (FIR) filter

Various techniques permit more thorough development of digital systems and devices by designers while protecting the proprietary interests of the owners of the intellectual property incorporated in such systems and devices. More specifically, the present invention provides to an end customer IP hardware which is suitable for prototype testing, but unusable for production purposes. One method limits the physical or electrical mode of operation of a hardware platform used for prototype testing of intellectual property (such as limiting the number of electrical contacts between the hardware and an external electrical device or limiting the data format(s) usable in the hardware during prototype testing). Another method limits the temporal operation of a hardware platform using an internal counter within the software provided by the intellectual property owner. Once a clock count limit is reached, the software disables the hardware in one or more prescribed ways, such as a reset of one or more registers, a global tri-state of the hardware IO, or a random failure of some type. Suitable hardware fabrication and/or augmentation also may be used to differentiate between the prototype and production manners of operation.

Method and apparatus for providing protected intellectual property

A method, apparatus and a filter compiler system for building a filter is disclosed. The filter compiler system includes a filter resource estimator. The filter resource estimator is configured to estimate an implementation cost of the filter. The filter compiler system determines whether the implementation cost is acceptable and updates a design of the filter upon determining that the implementation cost is unacceptable.

Finite impulse response (FIR) filter compiler for estimating cost of implementing a filter

Various techniques permit more thorough development of digital systems and devices by designers while protecting the proprietary interests of the owners of the intellectual property incorporated in such systems and devices. More specifically, the present invention provides to an end customer IP hardware which is suitable for prototype testing, but unusable for production purposes. One method limits the physical or electrical mode of operation of a hardware platform used for prototype testing of intellectual property (such as limiting the number of electrical contacts between the hardware and an external electrical device or limiting the data format(s) usable in the hardware during prototype testing). Another method limits the temporal operation of a hardware platform using an internal counter within the software provided by the intellectual property owner. Once a clock count limit is reached, the software disables the hardware in one or more prescribed ways, such as a reset of one or more registers, a global tri-state of the hardware, or a random failure of some type. Suitable hardware fabrication and/or augmentation also may be used to differentiate between the prototype and production manners of operation.

Methods and apparatus automate creation of code for system level simulations from hardware representations, specifically RTL representations. In one approach, individual RTL hardware modules are analyzed to generate code for corresponding system level modules. This is accomplished by taking a mapped netlist for a register transfer level (RTL) representation of the hardware module and converting it to what can be termed a 'system level netlist.' This system level netlist contains 'system level instances' corresponding to &#x201c;hardware cells&#x201d; of the mapped netlist. A mapped netlist includes hardware cells corresponding to programmed hardware units of a target hardware device. The method generates corresponding functional representations (code for system level simulation) from these hardware cells. This functional representation is referred to herein as a system level instance. System level instances are generated for each of the hardware cells in a given hardware module.

System level simulation models for hardware modules

A method, apparatus and system for building a filter is disclosed. In a particular embodiment, the filter is a finite impulse response (FIR) filter and a compiler suitable for implementing the FIR filter is described. The compiler includes a filter coefficient generator suitably arranged to provide a first set of filter coefficients corresponding to the desired FIR filter spectral response and a filter spectral response analyzer coupled to the filter coefficient generator for providing an expected FIR filter spectral response based in part upon the first set of filter coefficients. The compiler also includes a filter resource estimator coupled to the filter spectral response simulator for estimating an implementation cost of the FIR filter based upon the second set of filter coefficients as well as a filter compiler unit coupled to the resource estimator arranged to compile a FIR filter implementation output file.

Finite impulse response (FIR) filter compiler

Digital-to-analog and analog-to-digital conversion are implemented in or using programmable logic. The DAC and ADC circuits may be hardwired in a programmable logic integrated circuit or may be implemented using an intellectual property (IP) core. The IP core would be a series of bits to configure the logic cells and other programmable logic of an integrated circuit to include one or more DACs or ADC, or both on the same integrated circuit. The DAC may be a sigma-delta-modulator-based implementation or a resistor-ladder-based implementation.

Data converters for programmable logic

A complete hardware design environment is available through a system level simulator. This hardware design environment provides a bit accurate simulator for carrying out hardware simulations in the system level simulator. These simulations take advantage of the computational capabilities of the simulation processor. To take advantage of the simulation processor's resources (e.g., certain FPU components), the signals used in the simulation are made to conform to the native word type of the simulation processor. The hardware blocks deployed in a design frequently use non-native (from the simulation processor's perspective) word types. The bit accurate simulator casts words (signals) defined in the hardware design from a non-native format to a multi-bit native format suitable for use by the simulation processor. At various stages in the simulation, the simulator checks the 'value' of the signal to determine whether that value is allowed by a word format specified by the hardware design.

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Sunnyvale, CA, United States of America

Tony San