Agere Systems Inc.

Agere Systems Guardian Corp.

Lucent Technologies Inc.

Lsi Corporation

Avago Technologies General IP (Singapore) Pte. Ltd.

Tony S El-Kik

Donald Raymond Laturell

Steven Brooke Witmer

Keith Eugene Hollenbach

Anthony W Seaman

Raja Banerjea

Lane Allen Smith

William P Cornelius

Jeffrey Paul Grundvig

Thomas Baker

Kannan Rajamani

Richard Muscavage

Parag Parikh

Stefan Allen Siegel

Bahman Barazesh

Laurence Edward Bays

Richard Niescier

Dennis A Brooks

Stephen A Masnica

A method of performing digital division includes right-shifting a divider to provide a temporary divider, subtracting the temporary divider from a temporary dividend to provide a difference, determining the temporary dividend based on at least one of a dividend and the difference, and left-shifting a quotient based on the difference. A corresponding computer-readable medium and device are provided. A system to perform digital division includes a counter and a division circuit. The counter provides a count, and the division circuit is operatively coupled to the counter. The division circuit divides a dividend by a divider to provide a quotient in response to the counter. At least one of the counter and division circuit is configured to accept at least one of the count, dividend, divider, and quotient with a configurable bit-width.

Parameterized digital divider

A pulse synchronizer circuit converts an input data signal generated under a source-clock domain into an output data signal under a destination-clock domain, where the destination clock is independent of the source clock. The pulse synchronizer circuit successfully converts each data pulse in the input data signal into a corresponding data pulse in the output data signal when the source clock is faster than the destination clock, when the source clock is slower than the destination clock, when an input data pulse has a duration of one source-clock cycle, and when an input data pulse has a duration of multiple source-clock cycles. The pulse synchronizer circuit has source-domain circuitry and destination-domain circuitry. The source-domain circuitry detects input data pulses and determines whether they are single- or multi-cycle data pulses. The destination-domain circuitry generates output data pulses based on the processing of the source-domain circuitry.

Pulse synchronizer circuit

Methods and apparatus are provided for digital phase detection with improved frequency locking. A phase detector is disclosed for evaluating a phase difference between a clock signal and a reference signal. The disclosed phase detector samples the clock signal and the reference signal on positive edges of one or more of the clock signal and the reference signal, samples the clock signal and the reference signal on negative edges of one or more of the clock signal and the reference signal, and generates one or more error signals indicating a phase difference between the clock signal and the reference signal. A clock signal that is phase aligned with a reference signal can be generated by generating an error signal indicating a phase difference between the clock signal and the reference signal and applying the error signal to an oscillator to produce the clock signal.

Methods and apparatus for digital phase detection with improved frequency locking

A signal buffering and retiming (SBR) circuit for a plurality of memory devices. A PLL-based clock generator generates a set of phase-shifted clock signals from a received host clock signal. Each of a plurality of phase selectors independently selects a subset of contiguous clock signals from the set of phase-shifted clock signals. Each subset of contiguous clock signals is applied to a different set of one or more verniers, each vernier independently selecting one of the contiguous clock signals as its retiming clock signal for use in generating either (1) an output clock signal or a retimed bit of address or control data for one or more of the memory devices or (2) a feedback clock signal for the PLL-based clock generator. The SBR circuit can be designed to satisfy relatively stringent signal timing requirements related to skew and delay.

Signal buffering and retiming circuit for multiple memories

A digital filtering apparatus and method for digitally filtering out undesirable or invalid data from data signal lines. The digital filtering apparatus includes a digital delay element having one or more outputs, a comparator connected to the outputs of the digital delay element, and a final stage connected to the output of the comparator and the outputs of the digital delay element. The digital filtering apparatus recognizes and filters out invalid data from data received by the digital delay element, and allows valid data to pass through the filter. Data is considered invalid data if its logical data state transition has a duration less than the clock setting of the digital filtering apparatus. The clock setting can be established by the number of active delay components in the digital delay element. The inventive digital filtering apparatus represents an improvement over conventional analog filters, e.g., in manufacturing efficiency and filtering performance.

Apparatus and method for digitally filtering spurious transitions on a digital signal

A method and apparatus implementing an enhanced protocol between an I2C master and an I2C slave. In various embodiments the invention permits greater addressability space and high priority access to the slave device. The enhanced protocol is implemented by the addition of command code data being transmitted which is recognized through an interface circuit inside the slave device. The invention provides an I2C solution for accessing high priority address space with one command byte, medium priority space with two command bytes and low priority space with three command bytes.

Method and apparatus for providing an inter integrated circuit interface with an expanded address range and efficient priority-based data throughput

A control circuit and method for controlling the electrical characteristics of an input/output (I/O) circuit such as an output driver to account for variations in fabrication process, supply voltage, and/or temperature (PVT) conditions includes a PVT controller having appropriate control logic to permit PVT compensation to be observed, tested, and selectively adjusted. The PVT controller permits selection between PVT sensing circuit-provided control signals and control signals stored in a hardware register for controlling drive strength. The PVT controller further provides the capability to offset the selected drive strength by a fixed amount and select whether or not the offset is applied and permits full testability and observability of the selected control signal, an offset value applied thereto, and the resulting output signal.

Adjusting settings of an I/O circuit for process, voltage, and/or temperature variations

The invention is a method and apparatus for minimizing power consumption in a computer peripheral device during suspend state and waking up from suspend state without losing pre-suspend configuration information. The power supply to the peripheral device is split into two power rails, namely, a first rail that is unswitched and a second rail that is switched. The switched power rail provides power to components of the peripheral device other than the bus interface circuit. The unswitched power rail provides power to the bus interface circuit. When the device enters suspend mode, first power is removed from the components other than the bus interface circuit, then all outputs from the other components of the peripheral device to the bus interface circuit and all of the outputs from the bus interface circuit to the other components are forced to logic level 0 so that they do not float during suspend mode, and then finally the clock is disabled. When the device wakes up, power is first restored to the components, then the clock is turned on, and finally the outputs of the various components are released from logic level 0.

Method and apparatus for minimizing power requirements in a computer peripheral device while in suspend state and returning to full operation state without loss of data

A network interface circuit that screens out transient signals and provides an indication to the line side that an actual event has occurred, so that appropriate discrimination circuitry is powered up to determine the exact nature of the actual event only when actually needed. The present invention develops an AC signal that represents the events that are desired to be detected. This AC signal is timed so that it has a sustained rate (e.g., a 1 millisecond burst) that is unlike any transient that would occur on the line. Thus, unless the incoming signal meets the timing requirements of the circuit, it is disregarded as a being a transient and no action is taken to determine the exact nature of the signal. This avoids the need to invoke the discrimination circuits that have large power requirements until they are actually needed.

Event detection circuit

A circuit compensating for the difference in transmission rate of digital samples generated in transmit and receive paths between a user and a transceiver processing in the frequency domain, such as a digital multi-tone (DMT) transceiver. Compensation of the DMT transmission rate in the receive path in accordance with exemplary embodiments of the present employs zero-padding of the frequency domain coefficients generated by the DMT transceiver prior to applying an inverse transform, such as the inverse fast Fourier transform (IFFT). Zero-padding the frequency domain coefficients allows for the compensation of the transmission rate in the receive path by generating digital samples from the frequency domain coefficients with an inverse transform having a rate matched to the frequency domain transform and rate employed in the transmit path.

Transmission rate compensation for a digital multi-tone transceiver

A digital clock rate multiplier for multiplying the clock rate of an input signal to produce a multiplied output signal having a higher clock rate than the input signal. The digital clock rate multiplier includes a digital delay signal generator for developing first and second delay signals based on the input signal and a delayed version of the input signal, and a clock circuit for producing the multiplied output signal based at least partially on the first and second delay signals. The multiplied output signal may be used in high speed integrated circuits.

Digital clock rate multiplier method and apparatus

A telephone line interface circuit with event detection capabilities is provided that screens out transient signals and provides an indication to the line side that an actual event has occurred; so that appropriate discrimination circuitry is powered up to determine the exact nature of the actual event only when needed. An event detector develops an AC signal that represents the events to be detected. This AC signal is timed to determine its sustained rate. The sustained rate has a timing threshold which is higher than a transient that occurs on the line. If the incoming signal does not meet the required threshold timing, it is disregarded as being transient and no action is taken. If the incoming signal meets the threshold requirement, the line interface circuit switches to the full power mode and facilitates the actual data transmission.

Line interface circuit with event detection signaling

The use of a JTAG port for boundary scan testing of integrated circuits, (IC) thereby allowing for the testing of the IC's after they have been mounted onto a circuit board. The present invention speeds the testing of integrated circuitry by introducing an external memory where all the test vectors are stored. This external memory is connected to the digital processor core by a high speed interface extended memory interface (EMI). The test vectors are uploaded into the digital processor core from the external memory via the high speed EMI interface.

Integrated circuit testing using a high speed data interface bus

The present invention provides a synchronizing data protocol comprising one or more serial input-output (SIO) control word(s) and data passed across a high voltage interface, to allow the elimination of a frame synchronization signal (and corresponding AC coupling capacitors). The present invention has particular applicability to, e.g., time division multiplexed (TDM) data, serial data communication devices, or synchronous serial communication interfaces in general, and to the communication between a controller and a codec in an audio codec device in accordance with the AC '97 Specification, i.e., the AC Link. The synchronizing data protocol is implemented over a transmit data signal line to provide occasional synchronization (i.e., not frame-by-frame synchronization) between the two communicating devices. The master device includes a preamble insertion module to insert a predetermined preamble code word into the transmitted data stream. An interrupt is sent to the slave device by withholding the data clock signal for a predetermined amount of time. Upon receipt of the interrupt, the slave device monitors the data stream for the presence of the preamble code word. Upon detection of the preamble code word, data transmitted by the codec is again enabled.

Synchronizing data transfer protocol across high voltage interface

An apparatus for developing internal ROM code is disclosed for use in applications where software code is being developed for a ROM device inside a device and there is a need for the application to cause code from an external memory to be executed at the same time as internal ROM code. Accessing code from an external memory requires the use of the external bus interface. In order to free the external memory for use and the external bus interface for accessing code from external memory yet still allow testing of ROM code from an external memory before it is implemented on a ROM chip inside the device, an additional memory is used outside the device, and internal control logic is added.

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Allentown, PA, United States of America

Tony S El-Kik