Texas Instruments Corporation

International Business Machines Corporation

Burr-brown Corporation

Tony Ray Larson

Dimitar Trifonov

Allen A Bahr

David A Heisley

Rajen Manicon Murugan

Yiqi Tang

Larry LeeRoy Tretter

Jerry Doorenbos

Enis Tuncer

John Paul Tellkamp

Keith Ryan Green

Satyendra Singh Chauhan

Jie Chen

Usman Mahmood Chaudhry

Biraja Prasad Dash

Ming Li

Chao-Hsiuan Tsay

Partha Sarathi Basu

Rodney T Burt

Zhongyan Sheng

R Mark Stitt, Ii

Gerald William Steele

Srikanth Vellore Avadhanam Ramamurthy

James Becker

John C Teel

Mohammad-Reza Ghotbi

Raymond S Taylor

An integrated circuit includes a doped region having a first conductivity type formed in a semiconductor substrate having a second conductivity type. A dielectric layer is located between the doped region and a surface plane of the semiconductor substrate, and a polysilicon layer is located over the dielectric layer. First, second, third and fourth terminals are connected to the doped region, the first and third terminals defining a conductive path through the doped region and the second and fourth terminals defining a second conductive path through the doped region, the second path intersecting the first path.

Silicon hall sensor with low offset and drift compensation coils

A dual integrator system comprises two integrators, an output stage, and a switching network. The first and second integrators receive a differential Hall sensor signal and a reference voltage. The first integrator outputs a first integrator signal based on the differential Hall sensor and the reference voltage. The second integrator outputs a second integrator signal based on the differential Hall sensor signal and the reference voltage. The first integrator comprises a first offset cancellation feedback loop, and the second integrator comprises a second offset cancellation feedback loop. The switching network is coupled to the first and second integrators and to the output stage, and alternates which of the first and second integrators is coupled to the output stage. In some embodiments, the first and second integrators each perform a reset operation, a sampling operation, an integration operation, a differential to single-ended conversion operation, and a holding operation.

Switched capacitor integrator circuit with reference, offset cancellation and differential to single-ended conversion

A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including&#x2265;1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to &#x2265;1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.

Hall-effect sensor package with added current path

A semiconductor device includes first and second Hall-effect sensors. Each sensor has first and third opposite terminals and second and fourth opposite terminals. A control circuit is configured to direct a current through the first and second sensors and to measure a corresponding Hall voltage of the first and second sensors. Directing includes applying a first source voltage in a first direction between the first and third terminals of the first sensor and applying a second source voltage in a second direction between the first and third terminals of the second sensor. A third source voltage is applied in a third direction between the second and fourth terminals of the first sensor, and a fourth source voltage is applied in a fourth direction between the second and fourth terminals of the second sensor. The third direction is rotated clockwise from the first direction and the fourth direction rotated counter-clockwise from the second direction.

Hall-effect sensor with reduced offset voltage

A system comprises a calibration current generator, which provides a calibration current to a first and a second Hall channel, and a bias current generator, which determines a difference between a calibration signal from the Hall channels and a threshold and adjusts a biasing current for the Hall channels based on the difference. In some embodiments, the bias current generator comprises a subtractor coupled to an ADC and a controller coupled between the ADC and a DAC. The subtractor obtains a first and a second signal from the first and second Hall channels, respectively, and subtracts the first from the second to obtain the calibration signal. The controller determines the difference between a sampled signal from the ADC and the threshold and an adjustment to the biasing current based on the difference. The DAC adjusts the biasing current based on a control signal from the controller indicating the adjustment.

System for continuous calibration of hall sensors

A Hall-effect sensor package includes and an IC die including a Hall-Effect element and a leadframe including leads on a first side providing a first field generating current (FGC) path including &#x2265;1 first FGC input pin coupled by a reduced width first curved head over or under the Hall-effect sensor element to &#x2265;1 first FGC output pin, and second leads on a second side of the package. Some leads on the second side are attached to bond pads on the IC die including the output of the Hall-effect element. A clip is attached at one end to the first FGC input pin and at another end to a location on the first FGC output pin, having a reduced width second curved head in between that is over or under the Hall-effect sensor element opposite the first head.

Embodiments relate to a chopped amplifier system where a ripple reduction filter placed outside of a main signal path is disclosed. The chopped amplifier system includes a chopped amplifier having an input terminal and an output terminal, where the input terminal receives an input signal and the output terminal provides an output signal including a ripple that is based on an offset voltage of the chopped amplifier. The ripple reduction filter is placed in a feedback loop path that receives a portion of the chopped amplifier's output signal and provides a feedback signal to the chopped amplifier that reduces the ripple at the output of the chopped amplifier. The ripple reduction filter includes a digital controller and other circuits that can handle large disturbances such as large signal slew rate events and large common-mode steps without reducing the effectiveness of the ripple reduction filter in reducing the ripple.

Ripple reduction filter for chopped amplifiers

An apparatus includes a light source to generate source light through an optically transmissive medium to an object. A receiver includes a near zone light sensor and a far zone light sensor positioned on a substrate with the light source. The near zone light sensor is positioned on the substrate to, in response to the generated source light, receive reflected source light from the object and the optically transmissive medium. The far zone light sensor is positioned on the substrate to, in response to the source light, receive the reflected source light from the object and to receive a reduced quantity of the reflected source light from the optically transmissive medium compared to the near zone light sensor.

Multi-sensor proximity sensing using a near zone light sensor and a far zone light sensor

A hot swap controller includes a shunt resistor (-) and a power transistor (-) having a source coupled to a load maintains the first power transistor in a fully-turned-on condition to cause it to deliver a load current contribution (I) which flows through the shunt resistor and the power transistor to the load (). Current sensing circuitry (-) produces a first control signal (V-V) equal to the difference between a DC component (V) proportional to a first load current contribution (I) flowing in the first shunt resistor and a feedback-based component (V). A control amplifier (-) produces a second control signal (V) in response to the first control signal to modify a drive signal (-) to the power transistor so as to reduce a channel resistance of the power transistor if the first control signal exceeds a predetermined level.

Minimum loss and wiring circuit and method for paralleling hot swap controllers

Multiplier circuitry includes first multiplier circuit including a first transistor having an emitter coupled to a first conductor, a base coupled to a second conductor, and a collector coupled to a third conductor, a second transistor having an emitter coupled to the first conductor, a base coupled to a fourth conductor, and a collector coupled to a fifth conductor, a third transistor having an emitter coupled to the second conductor and a base and collector coupled to a supply voltage, and a fourth transistor having an emitter coupled to the fourth conductor and a base and collector coupled to the supply voltage. Chopper includes a first switch to provide a chopped differential signal between the second and fourth conductors and a second switch for un-chopping a first differential output signal produced between the third and fifth conductors to provide an un-chopped differential output signal between the third and fifth conductors.

Analog multiplier and method for current shunt power measurements

A programmable offset amplifier includes first (M) and second (M) input transistors having differentially connected sources and gates coupled to first (Vin) and second (Vin) input voltages. A tail current (I) is shared between the first and second input transistors. First (M) and second (M) load devices are coupled between a reference voltage and drains of the first and second input transistors, respectively. An output stage () has a first input (+) coupled to the drain of the second input transistor and a second input (&#x2212;) coupled to the drain of the first input transistor. Programmable voltage changes are produced on input elements of programmable input offset circuitry to cause changes in offset voltages associated with electrodes of the input transistors which are reflected back to the amplifier input to provide a large programmable input-referred offset voltage.

Low-noise, wide offset range, programmable input offset amplifier front end and method

An instrumentation amplifier includes first (A) and second (A) input amplifiers having outputs (A,B) coupled to an output amplifier (). A first auto-zero stage () in the first input amplifier is auto-zeroed to a first voltage level (V), a first input signal (Vin) is amplified by a second auto-zero stage () in the first input amplifier, and the amplified first input signal is coupled to the output amplifier, during a first phase (A). A third auto-zero stage () in the second input amplifier is auto-zeroed to a second voltage level (V), a second input signal (Vin) is amplified by a fourth auto-zero stage () in the second input amplifier, and the amplified second input signal is coupled to the output amplifier, during a second phase (B). The second auto-zero stage is auto-zeroed to the first voltage level, the first input signal is amplified by the first auto-zero stage (), and the amplified first input signal is coupled to the output amplifier, during a third phase (C). The fourth auto-zero stage is auto-zeroed to a the second voltage level, the second input signal is amplified by the third auto-zero stage, and the amplified second input signal is coupled to the output amplifier, during a fourth phase (D).

Low glitch offset correction circuit for auto-zero sensor amplifiers and method

A bandgap reference circuit as may be used in ultra-low current applications is provided. An exemplary bandgap circuit can be configured to generate a positive temperature coefficient without the need for a resistor to offset a negative temperature coefficient. In accordance with an exemplary embodiment of the present invention, a bandgap circuit comprises a negative temperature coefficient generated from a junction device and a positive temperature coefficient generated from an FET-based device. An exemplary junction device can comprise a bipolar, junction diode or any other device for generating a negative temperature coefficient, while an exemplary FET-based device comprises a gate-drain connected device configured to provide a gate-source voltage having a positive temperature coefficient coupled in series with the bipolar device. In accordance with another exemplary embodiment, the bandgap circuit can be configured with a threshold voltage elimination device comprising a second FET-based device configured to subtract out a threshold voltage component of the first FET-based device.

Bandgap reference circuit for ultra-low current applications

A low drop-out (&ldquo;LDO&rdquo;) voltage regulator includes an output stage of having a pass device and a discharge device arranged in complementary voltage follower configurations to both source load current to and sink load current from a regulated output voltage conductor. The pass device and the discharge device are controlled through a single feedback loop.

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Tucson, AZ, United States of America

Tony Ray Larson