Intermolecular, Inc.

Kabushiki Kaisha Toshiba

Applied Materials, Inc.

Sandisk 3d LLC

Novellus Systems Incorporated

Other

Angstron Systems, Inc.

Elpida Memory, Inc.

University of California

Elpidia Memory, Inc.

Intermoecular, Inc.

Angstrom Systems, Inc.

Tony P Chiang

Prashant B Phatak

Yun Yu Wang

Imran Hashim

Chi-I Lang

Peijun Ding

Pragati Kumar

Sandra Guy Malhotra

Barry Lee Chin

David E Lazovsky

Sunil Shanker

Dipankar Pramanik

Jinhong Tong

Michael A Miller

Alexander A Gorer

Thomas R Boussie

Sean Barstow

Nitin Kumar

Zhi-Wen Sun

Karl Frederick Leeser

Zheng Xu

Fusen E Chen

Tim Minvielle

Hong Zhang

Gongda Yao

Gene Y Kohara

Takeshi Yamaguchi

Kurt H Weiner

Majid Keshavarz

Wen Wu

Jianming Fu

Anh Duong

Vidyut Gopal

Zachary M Fresco

Ronald John Kuse

James Tsung

Bingxi Sun

Tanmay Kumar

Igor C Ivanov

April Dawn Schricker

Howard H Tang

Mankoo Lee

Bob Kong

Richard Endo

Jeffrey A Brown

Jason E Babcoke

Indranil De

Hanhong Chen

Edward L Haywood

Anish Tolia

Yu D Cong

Gaurav Verma

Sergey V Barabash

Aaron T Francis

Suraj Rengarajan

John M Schmidt

Nobi Fuchigami

Wayne R French

John C Forster

Xianmin Tang

Karl Anthony Littau

Praburam Gopalraja

Milind Ganesh Weling

Wim Deweerd

Xiying Costa

Chen-An Chen

Hong Sheng Yang

Tse-Yong Yao

Venkat Ananthan

Albert Sanghyup Lee

Ryan C Clarke

Charlene Chen

Jason Wright

Chi-l Lang

Guarav Verma

Xiyang Chen

Vijay Kris Narasimhan

Stephen Weeks

Martin Romero

Anna Tsizelmon

Jian Li

Guizhen Zhang

Robert A Huertas

Frank Greer

Randall Higuchi

Chandra V Deshpandey

Chien-Lan Hsueh

Gustavo A Pinto

Xiying Chen

Shouqian Shao

Sandip Niyogi

Yoram Schwarz

Kent Riley Child

Nobumichi Fuchigami

Upendra Avachat

Craig Hunter

Jane P Chang

Jihong Tong

Thomas H McWaid

Provided are novel compositions of current compliance layers (CCLs) as well as novel methods of fabricating such CCLs and novel architectures of arranging CCLs and memory cells in memory arrays. A CCL may comprise one of sulfur (S), selenium (Se), and tellurium (Te). The CCL may further comprise one of germanium (Ge) and silicon (Si). CCLs may be fabricated as amorphous structure and remain amorphous when heated to 400&#xb0; C. or 450&#xb0; C. and above. In some embodiments, CCLs have crystallization temperatures of greater than 400&#xb0; C. and, in some embodiments, glass transition temperatures of greater than 400&#xb0; C. CCLs may be fabricated using atomic layer deposition (ALD) as a nanolaminate of layers having different compositions. The composition, number, and arrangement of the layers in the nanolaminate is specifically selected to yield a desired composition of CCL.

Current compliance layers and memory arrays comprising thereof

We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer. A first protective layer of material is deposited on a substrate surface using traditional sputtering or ion deposition sputtering, in combination with sufficiently low substrate bias that a surface onto which the layer is applied is not eroded away or contaminated during deposition of the protective layer. Subsequently, a sculptured second layer of material is applied using ion deposition sputtering at an increased substrate bias, to sculpture a shape from a portion of the first protective layer of material and the second layer of depositing material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces.

Method for depositing a diffusion barrier layer and a metal conductive layer

Provided are nonvolatile memory assemblies each including a resistive switching layer and current steering element. The steering element may be a transistor connected in series with the switching layer. Resistance control provided by the steering element allows using switching layers requiring low switching voltages and currents. Memory assemblies including such switching layers are easier to embed into integrated circuit chips having other low voltage components, such as logic and digital signal processing components, than, for example, flash memory requiring much higher switching voltages. In some embodiments, provided nonvolatile memory assemblies operate at switching voltages less than about 3.0V and corresponding currents less than 50 microamperes. A memory element may include a metal rich hafnium oxide disposed between a titanium nitride electrode and doped polysilicon electrode. One electrode may be connected to a drain or source of the transistor, while another electrode is connected to a signal line.

Embedded nonvolatile memory elements having resistive switching characteristics

Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. In some embodiments, the selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a high leakage dielectric layer sandwiched between two lower leakage dielectric layers. The low leakage layers can function to restrict the current flow across the selector device at low voltages. The high leakage dielectric layer can function to enhance the current flow across the selector device at high voltages.

Current selector for non-volatile memory in a cross bar array based on defect and band engineering metal-dielectric-metal stacks

Resistive switching nonvolatile memory elements are provided. A metal-containing layer and an oxide layer for a memory element can be heated using rapid thermal annealing techniques. During heating, the oxide layer may decompose and react with the metal-containing layer. Oxygen from the decomposing oxide layer may form a metal oxide with metal from the metal-containing layer. The resulting metal oxide may exhibit resistive switching for the resistive switching memory elements.

Methods for forming resistive switching memory elements by heating deposited layers

We disclose a method of applying a sculptured layer of material on a semiconductor feature surface using ion deposition sputtering, wherein a surface onto which the sculptured layer is applied is protected to resist erosion and contamination by impacting ions of a depositing layer, A first protective layer of material is deposited on a substrate surface using traditional sputtering or ion deposition sputtering, in combination with sufficiently low substrate bias that a surface onto which the layer is applied is not eroded away or contaminated during deposition of the protective layer. Subsequently, a sculptured second layer of material is applied using ion deposition sputtering at an increased substrate bias, to sculpture a shape from a portion of the first protective layer of material and the second layer of depositing material. The method is particularly applicable to the sculpturing of barrier layers, wetting layers, and conductive layers upon semiconductor feature surfaces.

Methods for sealing a porous dielectric are presented including: receiving a substrate, the substrate including the porous dielectric; exposing the substrate to an organosilane, where the organosilane includes a hydrolysable group for facilitating attachment with the porous dielectric, and where the organosilane does not include an alkyl group; and forming a layer as a result of the exposing to seal the porous dielectric. In some embodiments, methods are presented where the organosilane includes: alkynyl groups, aryl groups, fluoroalkyl groups, heteroaryl groups, alcohol groups, thiol groups, amine groups, thiocarbamate groups, ester groups, ether groups, sulfide groups, and nitrile groups. In some embodiments, method further include: removing contamination from the porous dielectric and a conductive region of the substrate prior to the exposing; and removing contamination from the conductive region after the forming.

Molecular self-assembly in substrate processing

This disclosure provides a nonvolatile memory device and related methods of manufacture and operation. The device may include one or more resistive random access memory (ReRAM) approaches to provide a memory device with more predictable operation. In particular, the forming voltage required by particular designs may be reduced through the use of a barrier layer, a reverse polarity forming voltage pulse, a forming voltage pulse where electrons are injected from a lower work function electrode, or an anneal in a reducing environment. One or more of these techniques may be applied, depending on the desired application and results.

Reduction of forming voltage in semiconductor devices

Embodiments of the invention generally relate to memory devices and methods for fabricating such memory devices. In one embodiment, a method for fabricating a resistive switching memory device includes depositing a metallic layer on a lower electrode disposed on a substrate and exposing the metallic layer to an activated oxygen source while heating the substrate to an oxidizing temperature within a range from about 300&#xb0; C. to about 600&#xb0; C. and forming a metal oxide layer from an upper portion of the metallic layer during an oxidation process. The lower electrode contains a silicon material and the metallic layer contains hafnium or zirconium. Subsequent to the oxidation process, the method further includes heating the substrate to an annealing temperature within a range from greater than 600&#xb0; C. to about 850&#xb0; C. while forming a metal silicide layer from a lower portion of the metallic layer during a silicidation process.

Method for forming metal oxides and silicides in a memory device

Multistate nonvolatile memory elements are provided. The multistate nonvolatile memory elements contain multiple layers. Each layer may be based on a different bistable material. The bistable materials may be resistive switching materials such as resistive switching metal oxides. Optional conductor layers and current steering elements may be connected in series with the bistable resistive switching metal oxide layers.

Multistate nonvolatile memory elements

An embodiment of the present invention sets forth an embedded resistive memory cell that includes a first stack of deposited layers, a second stack of deposited layers, a first electrode disposed under a first portion of the first stack, and a second electrode disposed under a second portion of the first stack and extending from under the second portion of the first stack to under the second stack. The second electrode is disposed proximate to the first electrode within the embedded resistive memory cell. The first stack of deposited layers includes a dielectric layer, a high-k dielectric layer disposed above the dielectric layer, and a metal layer disposed above the high-k dielectric layer. The second stack of deposited layers includes a high-k dielectric layer formed simultaneously with the high-k dielectric layer included in the first stack, and a metal layer disposed above the high-k dielectric layer.

Creating an embedded ReRAM memory from a high-k metal gate transistor structure

A nonvolatile resistive memory element includes an oxygen-gettering layer. The oxygen-gettering layer is formed as part of an electrode stack, and is more thermodynamically favorable in gettering oxygen than other layers of the electrode stack. The Gibbs free energy of formation (&#x394;fG&#xb0;) of an oxide of the oxygen-gettering layer is less (i.e., more negative) than the Gibbs free energy of formation of an oxide of the adjacent layers of the electrode stack. The oxygen-gettering layer reacts with oxygen present in the adjacent layers of the electrode stack, thereby preventing this oxygen from diffusing into nearby silicon layers to undesirably increase an SiOinterfacial layer thickness in the memory element and may alternately be selected to decrease such thickness during subsequent processing.

Nonvolatile resistive memory element with an oxygen-gettering layer

Embodiments of the invention generally include a method of forming a nonvolatile memory device that contains a resistive switching memory element that has an improved device switching performance and lifetime, due to the addition of a current limiting component disposed therein. In one embodiment, the current limiting component comprises at least one layer of resistive material that is configured to improve the switching performance and lifetime of the formed resistive switching memory element. The electrical properties of the formed current limiting layer, or resistive layer, are configured to lower the current flow through the variable resistance layer during the logic state programming steps (i.e., 'set' and 'reset' steps) by adding a fixed series resistance in the formed resistive switching memory element found in the nonvolatile memory device. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players.

Nonvolatile memory device having a current limiting element

Methods for sealing a porous dielectric are presented including: receiving a substrate, the substrate including the porous dielectric; exposing the substrate to an organosilane, where the organosilane includes a hydrolysable group for facilitating attachment with the porous dielectric, and where the organosilane does not include an alkyl group; and forming a layer as a result of the exposing to seal the porous dielectric. In some embodiments, methods are presented where the organosilane includes: alkynyl groups, aryl groups, flouroalkyl groups, heteroarlyl groups, alcohol groups, thiol groups, amine groups, thiocarbamate groups, ester groups, ether groups, sulfide groups, and nitrile groups. In some embodiments, method further include: removing contamination from the porous dielectric and a conductive region of the substrate prior to the exposing; and removing contamination from the conductive region after the forming.

Growing community of inventors

Campbell, CA, United States of America

Tony P Chiang