Brocade Communications Systems, Inc.

Cisco Technology, Inc.

Brocade Communication Systems LLC

Tony Nguyen

Kung-Ling Ko

Prateek Sharma

Surya Parkash Varanasi

Joseph Juh-En Cheng

Christian Lemler

Jiang Jiang

Ye Thein

Wai-Ling Hew

Tuan Van Quach

Gregory S Walter

A switch according to the present invention can have a number of ports in an ASIC greater than the ASIC clock speed divided by the network protocol rate. The switch ASIC contains multiple blocks, each block having a number of ports equal to the ASIC clock speed divided the packet rate of the protocol. Each block has a number of queues equal to the total number of ports on the ASIC to receive packets. The queues are scheduled from each block into a number of outputs equal to the number of blocks. The outputs of each block are received by a scheduler which evaluates the packets available at the outputs of each block to determine the combination of outputs which provides the most connections that are ready for transmission. The combination with the most connections is then utilized to provide packets to the egress section of each block.

Most connection method for egress port selection in a high port count switch

A two-port memory having a read port, a write port and a plurality of identical single-port RAM banks. The capacity of one of the single-port RAM banks is used to resolve collisions between simultaneous read and write accesses to the same single-port RAM bank. A read mapping memory stores instance information that maps logical banks and a spare bank to the single-port RAM banks for read accesses. Similarly, a write mapping memory stores write instance information that maps logical banks and a spare bank to the single-port RAM banks for write accesses. If simultaneous read and write accesses are not mapped to the same single-port RAM bank, read and write are performed simultaneously. However, if a collision exists, the write access is re-mapped to a spare bank identified by the write instance information, allowing simultaneous read and write. Both read and write mapping memories are updated to reflect any re-mapping.

Two-port memory implemented with single-port memory blocks

A multi-host host bus adapter (HBA) can be connected to multiple host devices to allow the multiple host devices to communicate on a SAN fabric. More specifically, the multi-host HBA provides an interface for multiple SAN hosts without necessitating an HBA on each host, eliminating the need for an on-board HBA on each SAN host. The multi-host HBA interfaces to memory in each SAN host to which it is connected using PCI-Express (or a similar protocol), and communicates with other devices on the SAN fabric using Fibre Channel ports. The multi-host HBA communicates by receiving a command from a connected host, forwarding the command to a processor in the multi-host HBA, and sending the command to a device on a SAN. When the multi-host HBA receives a response from the device on the SAN, the multi-host HBA associates the response with the process and sends the response to the host.

Host bus adapter with multiple hosts

A method and apparatus are provided for aggregating flow records representing network flow. Specifically, flow records may be organized according to whether they are request records, response records associated with the request records, or flow records associated with neither category. A request record may represent a network flow to a particular device of a particular network flow type, for example, network flow to a standard port. The request records and flow records are then aggregated.

Aggregating information about network message flows

Growing community of inventors

San Jose, CA, United States of America

Tony Nguyen