Broadcom Corporation

Tony Michael Turner

Myron Buer

John Lupienski

Iue-Shuenn Chen

Robert Brownhill

Martin Kuhlmann

Jonathan Huy Kuo

Vin P Hue

Jack Arnold Manson

Methods and systems for processing multi-stage programming (MSP) bits within one-time-programmable (OTP) memory are disclosed herein. Aspects of the method may comprise determining whether at least one MSP memory bit in the OTP memory is programmed and whether a register bit associated with said at least one MSP memory bit is asserted. If the register bit is deasserted and the MSP memory bit is unprogrammed, the MSP memory bit may be programmed. The register bit in the OTP memory may be associated with the MSP memory bit. The MSP memory bit may be programmed to logic zero or logic one. If the register bit associated with the MSP memory bit is asserted, programming of the MSP memory bit may be blocked. The register bit associated with the MSP memory bit may be reset and it may be determined whether the MSP memory bit is accessed.

Method and system for locking OTP memory bits after programming

Methods and systems for extending the functionality of an embedded Universal Serial Bus (USB) transceiver interface to handle threshold shift of a USB 2.0 bus during high-speed chirp are presented. A method for a transceiver of a host coupled by a USB 2.0 bus to a device includes receiving a control signal, and selecting one of a first and second zero level voltage threshold according to the control signal. The first threshold is higher than the second to compensate for a shift in a zero level of the bus during high-speed chirp. In one example, the transceiver selects the first threshold when driving a reset signal, and selects the second threshold after detecting a device high-speed chirp signal. In another example, the transceiver selects the second threshold after driving a high-speed chirp sequence. In one example, the control signal includes a signal of a host controller embedded USB transceiver interface.

Method and system for extending the functionality of an embedded USB transceiver interface to handle threshold shift of a USB 2.0 bus during high-speed chirp

Aspects of a method and system for blocking data in scan registers from being shifted out of a device may comprise preventing data intrusion in an integrated circuit by generating a device reset signal prior to entering scan mode. The method may further comprise detecting an attempt to enter said scan mode. The device reset signal may also be an internal reset signal. A subsequent device reset signal may be generated after entering scan mode. The subsequent device reset signal may be an internal pulse signal. The method may further comprise clearing stored data in an integrated circuit after generating a subsequent device reset signal.

Method and system for blocking data in scan registers from being shifted out of a device

A multi-bit write pointer that is associated with a first clock can be converted to a single-bit write pointer. A multi-bit read pointer that is associated with a second clock can be converted to a single-bit read pointer. The first clock and the second clock are not synchronized. One or more guard bits can be associated with the single-bit write pointer and/or the single-bit read pointer. The single-bit write pointer and the single-bit read pointer can be compared. According to an embodiment, an error can be detected in response to comparing the single-bit write pointer and the single-bit read pointer.

Method and apparatus to compare pointers associated with asynchronous clock domains

A method of programming a memory includes the steps of attempting to program a bit at a designated address for a predetermined time; testing the bit to see if it has been programmed; increasing the predetermined time by approximately an order of magnitude; repeating the previous steps (until the bit at the designated address is programmed; and repeating all the previous steps by advancing the designated address until all bits in the memory are programmed.

Automatic programming time selection for one time programmable memory

A one time programmable memory circuit includes a one time programmable memory array. A write circuit outputs data to the one time programmable memory array. A power up write controller outputs the data and a write enable signal to the write circuit. A read circuit outputs data from the one time programmable memory array upon a read enable signal received from a read controller. An address decoder communicates with the power up write controller and the read controller, for providing an address to the one time programmable memory array.

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Foothill Ranch, CA, United States of America

Tony Michael Turner