Mosaid Technologies Corporation

Conversant Intellectual Property Management Incorporated

Tony Mai

Dieter Haerle

Peter Vlasenko

Bruce Millar

Susan Coleman

Seanna Pike

A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial delay, the delay is varied in one direction, forcing the DLL to skip the first lock point. The initialization circuitry only allows the DLL to vary the delay of the voltage controlled delay loop in the one direction from the initial delay until the operating point is reached.

Delay locked loop circuit and method

An initialization circuit in a delay locked loop ensures that after power up or other reset clock edges are received by a phase detector in the appropriate order for proper operation. After reset of the delay locked loop, the initialization circuit assures that at least one edge of a reference clock is received prior to enabling the phase detector to increase (or decrease) the delay in a delay line. After at least one edge of a feedback clock is received, the initialization circuit enables the phase detector to decrease (or increase) the delay in a delay line.

Initialization circuit for delay locked loop

Intialization circuit for delay locked loop

A biasing circuit for biasing differential delay elements is provided. The circuit is a feedback-free circuit consisting of a CMOS output stage having a P-type transistor and an N-type transistor, with a diode connected transistor between the P-type transistor and the N-type transistor, the output stage receiving the control voltage as input, and producing the Vbetween the P-type transistor and the diode connected transistor. The circuit is simpler than conventional biasing circuits that employ feedback and operational amplifiers.

Simplified bias circuitry for differential buffer stage with symmetric loads

An integrated power and clock grid which is capable of being placed and routed using ASIC software design tools. The integrated grid comprises three types of grid unit cells having power rails and clock lines. The power rails and clock lines comprise different orientations in the different grid unit cells.

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Kanata, Canada

Tony Mai