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Canadian Marconi Corporation

Tony M Costa

Robert Resuta

A convolutional decoder for decoding a received message of digital data convolutionally encoded at a constraint length of K, comprises branch metric calculating circuitry for receiving the data and providing output signals indicative of the branch metrics therefor, a plurality of 2.sup.K-1 circuits for receiving the output signals and computing state metrics, the circuits being interconnected to form a trellis and generating decision bits and a plurality of 2.sup.K-1 memory circuits, the memory circuits being interconnected also to form a trellis and responsive to the decision bits to output a decoded digit of the received message data.

High-speed convolutional decoder

A system for convolutional interleaving of data bits in accordance with preselected convolutional interleaving parameters employs random access memory (RAM) and control thereof is provided by WRITE and READ column and row signals, which are generated responsively to the interleaving parameters and permit realization of the system with memory requirements slightly more than shift register interleavers but substantially less than hetertofore known RAM interleaver implementations. In one system embodiment, the system output data bits involve both RAM output and the incoming data bit. In another system embodiment, pseudo random convolutional interleaving is attained, again responsively to the preselected convolutional interleaving parameters. In either system, the parameters may be changed as desired to accommodate performance need.

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Kearny, NJ, United States of America

Tony M Costa