Micron Technology Incorporated

Convey Computer

Chiaro Networks Ltd

Hewlett-packard Company

Foundry Networks, Inc.

Hewlett-packard Development Company, L.p.

Convex Computer Corporation

Jeremy Benjamin As Receiver for Chiaro Networks Ltd.

Tony M Brewer

Dean E Walker

Bryan D Hornung

David M Patrick

Gregory S Palmer

Michael K Dugan

Patrick Alan Estep

Steven Jeffrey Wallach

J Michael Andrewartha

Keith W Shaw

Harold Wallace Dozier

Thomas C McDermott, Iii

William D O'Leary

Jim Kleiner

Harry C Blackmon

Douglas John Vanesko

Skyler Arron Windh

Chris Baronne

Brian W Huber

David M Chastain

Michael Grassi

Miles S Wiscombe

Christopher A Baronne

Thomas Lee Watson

David Traylor

Brent Keeth

David Andrew Roberts

Scott Eugene Smith

Gary L Howe

Kirk D Pospesel

Michael G Placke

Lou Yeh

Chris Davies

Terrell Magee

John D Leidel

Allen Frank Rozman

David Boles

Joe Bolding

Kevin R Wadleigh

Paul F Vogel

Gongyu Wang

Kenneth Chaney

Mike Dugan

Roger Sunshine

Christopher P Davies

Scott E Smith

A chiplet-based system comprises a substrate including conductive interconnect and multiple chiplets arranged on the interposer and interconnected using the conductive interconnect of the substrate. A chiplet includes multiple columns of multiple input-output (I/O) channels and the I/O channels are connected to a block of I/O pads and each side of the chiplet includes multiple blocks of the I/O pads. The multiple blocks of I/O pads on the side of the chiplet are arranged symmetrically relative to a centerline of the chiplet and each block of I/O pads on the side of the chiplet is at a common distance from any adjacent block of I/O pads on the side.

Edge interface placements to enable chiplet rotation into multi-chiplet cluster

Devices and techniques for asynchronous event message handing in a processor are described herein. A barrel multithreaded processor may include an asynchronous event handler to receive an indication of a thread create instruction from a parent thread, determine a return value size of return values from the indication of the thread create instruction, determine whether sufficient space exists in the memory to store the return values, allocate space in the memory to store the return parameters in response to determining that there is sufficient space in the memory to store the return values, and provide access to the return values from the allocated space to the parent thread based at least in part on a thread return instruction from the child thread.

Queueing asynchronous events for acceptance by threads executing in a barrel processor

A system includes a host device having a first buffer with ordered data. An accelerator device has a data movement processor and a reordering buffer. A multiple-channel interface couples the host device and the data movement processor of the accelerator device. The data movement processor is configured to issue a read command for a portion of the ordered data. In coordination with issuing the read command, an entry of the reordering buffer is allocated. A transaction identifier for the read command is allocated. Unordered responses are received from the host device via the multiple-channel interface. The responses include respective portions of the ordered data and a respective transaction identifier. The responses are reordered in the reordering buffer based on the respective transaction identifiers and the allocated entry of the reordering buffer.

Access request reordering across a multiple-channel interface for memory-based communication queues

A system includes a memory device and a command manager configured to reorder read requests. The command manager is configured to receive a read response associated with a transaction identifier for the read request. A free list entry for the read request is allocated from a free list. The free list entry is associated with a transaction identifier of the read request. A tail index of a reordering queue is written to a remapping queue based on the free list entry. The tail index is configured to provide a write address of the reordering queue that is allocated for the read request. A read response associated with the transaction identifier for the read request is received. The read response is written to the allocated entry of the reordering queue.

Access request reordering for memory-based communication queues

Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory devices are configured to provide row clear features. In some embodiments, the memory device may receive a command from a host device directed to a row of a memory array included in the memory device. The memory device may determine that the command is directed to two or more columns associated with the row, where each column is coupled with a group of memory cells. The memory device may activate the row to write the two or more columns using a set of predetermined data stored in a register of the memory device. Subsequently, the memory device may deactivate the word line based on writing the set of predetermined data to the two or more columns.

Row clear features for memory devices and associated methods and systems

A cache memory can maintain multiple cache lines and each cache line can include a data field, an encryption status attribute, and an encryption key attribute. The encryption status attribute can indicate whether the data field in the corresponding cache line includes encrypted or unencrypted data and the encryption key attribute can include an encryption key identifier for the corresponding cache line. In an example, a cryptographic controller can access keys from a key table to selectively encrypt or unencrypt cache data. Infrequently accessed cache data can be maintained as encrypted data, and more frequently accessed cache data can be maintained as unencrypted data. In some examples, different cache lines in the same cache memory can be maintained as encrypted or unencrypted data, and different cache lines can use respective different encryption keys.

Selective cache line memory encryption

A system including a memory controller chiplet having a memory interface that is configured to couple the memory controller chiplet to first and second memory devices. The memory interface includes first and second memory channels having respective data widths, and configured to couple first and second I/O interfaces of the memory controller chiplet to an interface of the first memory device having a data channel width at least equal to the combined first and second memory channel widths, where the first and second memory channels have independent command/address (CA) paths; and third and fourth memory channels having respective data widths, and configured to couple third and fourth I/O interfaces of the memory controller chiplet to an interface of the second memory device having a data channel width at least equal to the combined third and fourth memory channel widths, wherein the third and fourth memory channels have independent CA paths.

Multiple channel memory system

To enable threads to self-schedule in a processor, when it is determined that an instruction will not complete within a threshold prior to insertion into a pipeline of the processor, a thread identifier (ID) can be passed with the instruction. Here, the thread ID corresponds to a thread of the instruction. When a response to completion of the instruction is received that includes the thread ID, the thread is rescheduled using the thread ID in the response.

Self-scheduling threads in a processor based on a threshold associated with pipeline stages

Disclosed in some examples are systems, methods, devices, and machine-readable mediums to detect and terminate programmable atomic transactions that are stuck in an infinite loop. In order to detect and terminate these transactions, the programmable atomic unit may use an instruction counter that increments each time an instruction is executed during execution of a programmable atomic transaction. If the instruction counter meets or exceeds a threshold instruction execution limit without reaching the termination instruction, the programmable atomic transaction may be terminated, all resources used (e.g., memory locks) may be freed, and a response may be sent to a calling processor.

Detecting infinite loops in a programmable atomic transaction

Devices and techniques for thread scheduling control and memory splitting in a processor are described herein. An apparatus includes a hardware interface configured to receive a first request to execute a first thread, the first request including an indication of a workload; and processing circuitry configured to: determine the workload to produce a metric based at least in part on the indication; compare the metric with a threshold to determine that the metric is beyond the threshold; divide, based at least in part on the comparison, the workload into a set of sub-workloads consisting of predefined number of equal parts from the workload; create a second request to execute a second thread, the second request including a first member of the set of sub-workloads; and process a second member of the set of sub-workloads in the first thread.

Dynamic decomposition and thread allocation

System and techniques for variable execution time atomic operations are described herein. When an atomic operation for a memory device is received, the run length of the operation is measured. If the run length is beyond a threshold, a cache line for the operation is locked while the operation runs. A result of the operation is queued until it can be written to the cache line. At that point, the cache line is unlocked.

Variable execution time atomic operations

Disclosed in some examples, are methods, systems, programmable atomic units, and machine-readable mediums that provide an exception as a response to the calling processor. That is, the programmable atomic unit will send a response to the calling processor. The calling processor will recognize that the exception has been raised and will handle the exception. Because the calling processor knows which process triggered the exception, the calling processor (e.g., the Operating System) can take appropriate action, such as terminating the calling process. The calling processor may be a same processor as that executing the programmable atomic transaction, or a different processor (e.g., on a different chiplet).

Method of notifying a process or programmable atomic operation traps

Representative apparatus, method, and system embodiments are disclosed for a self-scheduling processor which also provides additional functionality. Representative embodiments include a self-scheduling processor, comprising: a processor core adapted to execute a received instruction; and a core control circuit adapted to automatically schedule an instruction for execution by the processor core in response to a received work descriptor data packet. In another embodiment, the core control circuit is also adapted to schedule a fiber create instruction for execution by the processor core, to reserve a predetermined amount of memory space in a thread control memory to store return arguments, and to generate one or more work descriptor data packets to another processor or hybrid threading fabric circuit for execution of a corresponding plurality of execution threads. Event processing, data path management, system calls, memory requests, and other new instructions are also disclosed.

Thread commencement using a work descriptor packet in a self-scheduling processor

A credit return field is used in a credit-based flow control system to indicate that one or more credits are being returned to a sending device from a receiving device. Based on the number of credits available, the sending device determines whether to send device or wait until more credits are returned. A write enable mask allows a wide data field to be used even when a smaller amount of data is to be written. A novel data packet uses a combined write enable mask and credit return field. In one mode, the field contains a write enable mask. In another mode, the field contains credit return data. If the field contains credit return data, a default value (e.g., all ones) is used for the write enable mask. The mode may be selected based on another value in the data packet.

Combined write enable mask and credit return field

System and techniques for recall pending cache line eviction are described herein. A queue that includes a deferred memory request is kept for a cache line. Metadata for the queue is stored in a cache line tag. When a recall is needed, the metadata is written from the tag to a first recall storage, referenced by a memory request ID. After the recall request is transmitted, the memory request ID is written to a second recall storage referenced by the message ID of the recall request. Upon receipt of a response to the recall request, the queue for the cache line can be restored by using the message ID in the response to lookup the memory request ID from the second recall storage, then using the memory request ID to lookup the metadata from the first recall storage, and then writing the metadata into the tag for the cache line.

Recall pending cache line eviction

Growing community of inventors

Plano, TX, United States of America

Tony M Brewer