Micron Technology Incorporated

Convey Computer

Chiaro Networks Ltd

Hewlett-packard Company

Foundry Networks, Inc.

Hewlett-packard Development Company, L.p.

Convex Computer Corporation

Jeremy Benjamin As Receiver for Chiaro Networks Ltd.

Tony M Brewer

Dean E Walker

Bryan D Hornung

David M Patrick

Gregory S Palmer

Patrick Alan Estep

Michael K Dugan

Steven Jeffrey Wallach

J Michael Andrewartha

Keith W Shaw

Harold Wallace Dozier

Thomas C McDermott, Iii

William D O'Leary

Jim Kleiner

Harry C Blackmon

Douglas John Vanesko

Skyler Arron Windh

Chris Baronne

David M Chastain

Michael Grassi

Christopher A Baronne

Thomas Lee Watson

David Traylor

Brent Keeth

Scott Eugene Smith

Brian W Huber

Gary L Howe

Miles S Wiscombe

Kirk D Pospesel

Lou Yeh

Chris Davies

Terrell Magee

David Andrew Roberts

John D Leidel

Allen Frank Rozman

David Boles

Joe Bolding

Kevin R Wadleigh

Paul F Vogel

Gongyu Wang

Kenneth Chaney

Michael G Placke

Mike Dugan

Christopher P Davies

Roger Sunshine

A cache memory can maintain multiple cache lines and each cache line can include a data field, an encryption status attribute, and an encryption key attribute. The encryption status attribute can indicate whether the data field in the corresponding cache line includes encrypted or unencrypted data and the encryption key attribute can include an encryption key identifier for the corresponding cache line. In an example, a cryptographic controller can access keys from a key table to selectively encrypt or unencrypt cache data. Infrequently accessed cache data can be maintained as encrypted data, and more frequently accessed cache data can be maintained as unencrypted data. In some examples, different cache lines in the same cache memory can be maintained as encrypted or unencrypted data, and different cache lines can use respective different encryption keys.

Selective cache line memory encryption

A system including a memory controller chiplet having a memory interface that is configured to couple the memory controller chiplet to first and second memory devices. The memory interface includes first and second memory channels having respective data widths, and configured to couple first and second I/O interfaces of the memory controller chiplet to an interface of the first memory device having a data channel width at least equal to the combined first and second memory channel widths, where the first and second memory channels have independent command/address (CA) paths; and third and fourth memory channels having respective data widths, and configured to couple third and fourth I/O interfaces of the memory controller chiplet to an interface of the second memory device having a data channel width at least equal to the combined third and fourth memory channel widths, wherein the third and fourth memory channels have independent CA paths.

Multiple channel memory system

To enable threads to self-schedule in a processor, when it is determined that an instruction will not complete within a threshold prior to insertion into a pipeline of the processor, a thread identifier (ID) can be passed with the instruction. Here, the thread ID corresponds to a thread of the instruction. When a response to completion of the instruction is received that includes the thread ID, the thread is rescheduled using the thread ID in the response.

Self-scheduling threads in a processor based on a threshold associated with pipeline stages

Disclosed in some examples are systems, methods, devices, and machine-readable mediums to detect and terminate programmable atomic transactions that are stuck in an infinite loop. In order to detect and terminate these transactions, the programmable atomic unit may use an instruction counter that increments each time an instruction is executed during execution of a programmable atomic transaction. If the instruction counter meets or exceeds a threshold instruction execution limit without reaching the termination instruction, the programmable atomic transaction may be terminated, all resources used (e.g., memory locks) may be freed, and a response may be sent to a calling processor.

Detecting infinite loops in a programmable atomic transaction

Devices and techniques for thread scheduling control and memory splitting in a processor are described herein. An apparatus includes a hardware interface configured to receive a first request to execute a first thread, the first request including an indication of a workload; and processing circuitry configured to: determine the workload to produce a metric based at least in part on the indication; compare the metric with a threshold to determine that the metric is beyond the threshold; divide, based at least in part on the comparison, the workload into a set of sub-workloads consisting of predefined number of equal parts from the workload; create a second request to execute a second thread, the second request including a first member of the set of sub-workloads; and process a second member of the set of sub-workloads in the first thread.

Dynamic decomposition and thread allocation

System and techniques for variable execution time atomic operations are described herein. When an atomic operation for a memory device is received, the run length of the operation is measured. If the run length is beyond a threshold, a cache line for the operation is locked while the operation runs. A result of the operation is queued until it can be written to the cache line. At that point, the cache line is unlocked.

Variable execution time atomic operations

Disclosed in some examples, are methods, systems, programmable atomic units, and machine-readable mediums that provide an exception as a response to the calling processor. That is, the programmable atomic unit will send a response to the calling processor. The calling processor will recognize that the exception has been raised and will handle the exception. Because the calling processor knows which process triggered the exception, the calling processor (e.g., the Operating System) can take appropriate action, such as terminating the calling process. The calling processor may be a same processor as that executing the programmable atomic transaction, or a different processor (e.g., on a different chiplet).

Method of notifying a process or programmable atomic operation traps

Representative apparatus, method, and system embodiments are disclosed for a self-scheduling processor which also provides additional functionality. Representative embodiments include a self-scheduling processor, comprising: a processor core adapted to execute a received instruction; and a core control circuit adapted to automatically schedule an instruction for execution by the processor core in response to a received work descriptor data packet. In another embodiment, the core control circuit is also adapted to schedule a fiber create instruction for execution by the processor core, to reserve a predetermined amount of memory space in a thread control memory to store return arguments, and to generate one or more work descriptor data packets to another processor or hybrid threading fabric circuit for execution of a corresponding plurality of execution threads. Event processing, data path management, system calls, memory requests, and other new instructions are also disclosed.

Thread commencement using a work descriptor packet in a self-scheduling processor

A credit return field is used in a credit-based flow control system to indicate that one or more credits are being returned to a sending device from a receiving device. Based on the number of credits available, the sending device determines whether to send device or wait until more credits are returned. A write enable mask allows a wide data field to be used even when a smaller amount of data is to be written. A novel data packet uses a combined write enable mask and credit return field. In one mode, the field contains a write enable mask. In another mode, the field contains credit return data. If the field contains credit return data, a default value (e.g., all ones) is used for the write enable mask. The mode may be selected based on another value in the data packet.

Combined write enable mask and credit return field

System and techniques for recall pending cache line eviction are described herein. A queue that includes a deferred memory request is kept for a cache line. Metadata for the queue is stored in a cache line tag. When a recall is needed, the metadata is written from the tag to a first recall storage, referenced by a memory request ID. After the recall request is transmitted, the memory request ID is written to a second recall storage referenced by the message ID of the recall request. Upon receipt of a response to the recall request, the queue for the cache line can be restored by using the message ID in the response to lookup the memory request ID from the second recall storage, then using the memory request ID to lookup the metadata from the first recall storage, and then writing the metadata into the tag for the cache line.

Recall pending cache line eviction

Disclosed in some examples, are methods, systems, devices, and machine-readable mediums which provide for more efficient CGRA execution by assigning different initiation intervals to different PEs executing a same code base. The initiation intervals may be a multiple of each other and the PE with the lowest initiation interval may be used to execute instructions of the code that is to be executed at a greater frequency than other instructions than other instructions that may be assigned to PEs with higher initiation intervals.

Efficient processing of nested loops for computing device with multiple configurable processing elements using multiple spoke counts

Implementations of the present disclosure are directed to systems and methods for reducing design complexity and critical path timing challenges of credit return logic. A wide bus supports simultaneous transmission of multiple flits, one per lane of the wide bus. A source device transmitting flits on a wide bus selects from among multiple credit return options to ensure that only one of the multiple flits being simultaneously transmitted includes a credit return value. In some example embodiments, the receiving device checks only the flit of one lane of the wide bus (e.g., lane) for credit return data. In other example embodiments, the receiving device uses a bitwise-OR to combine the credit return data of all received flits in a single cycle.

Network credit return mechanisms

Methods, systems, and devices for shared virtual address spaces are described. In some examples, a globally shared address space may be shared across a plurality of memory devices that are included in one or more domains. A host system may set parameters for determining whether an address (e.g., a virtual address) is included within the globally shared address space, and whether the address is associated with a memory device. When a memory device receives a memory request (e.g., a data packet), a processing unit of the memory device may determine whether an address included in the memory request is associated with the memory device. The processing unit may either initiate an access operation on a physical address of the memory device or transmit the memory request to another memory device.

Shared virtual address spaces

A three-dimensional stacked integrated circuit (3D SIC) that can have at least a first 3D XPoint (3DXP) die and, in some examples, can have at least a second 3DXP die too. In such examples, the first 3DXP die and the second 3DXP die can be stacked. The 3D SIC can be partitioned into a plurality of columns that are perpendicular to each of the stacked dies. In such examples, when a first column of the plurality of columns is determined as failing, data stored in the first column can be replicated to a second column of the plurality of columns. Also, for example, when a part of a first column of the plurality of columns is determined as failing, data stored in the part of the first column can be replicated to a corresponding part of a second column of the plurality of columns.

3D stacked integrated circuits having functional blocks configured to provide redundancy sites

Methods, systems, and devices for virtual addresses for a memory system are described. In some examples, a virtual address space may be shared across a plurality of memory devices that are included in one or more domains. The memory devices may be able to communicate with each other directly. For example, a first memory device may be configured to generate a data packet that includes an identifier and an address that is included in the shared virtual address space. The data packet may be transmitted to a second memory device based on the identifier, and the second memory device may access a physical address based on the address.

Virtual addresses for a memory system

Growing community of inventors

Plano, TX, United States of America

Tony M Brewer