Canon Kabushiki Kaisha

Canon Information Systems, Inc.

Tony K Ip

William C Russell

Robert D Wadsworth

Walter D Kuver

Royce Earle Slick

Don Francis Purpura

Lorraine F Barrett

George A Kalwitz

Andrew J Kraslavsky

Wei Zhou

Daniel A Danknick

Gregory F Beck

Osman Ozay Oktay

H Brad Emerson

Elias Montenegro

Trent Lee England

Duc Tran

A digital video network interface for transferring isochronous video data over an asynchronous local area network, including an isochronous interface for transmitting digital video data isochronously, a memory comprising first and second buffers for storing the isochronous video data, a network interface for transmitting video data from either the first or second buffers over the asynchronous local area network, and a memory buffer manager for controlling the output of the video data over the asynchronous local area network and for controlling the input/output of video data into/from the first or second buffers, wherein, when either the first or second buffers is filled with video data, the memory buffer manager shifts the input of data into an empty buffer and begins outputting video data to the asynchronous local area network from a filled buffer, upon receiving access to the local area network. Complementary ones of such video network interfaces may be provided on a network so as to permit one-way video streaming (to one or more receiving sites) or two-way video conferencing with network interfaces operating in full-duplex mode.

Digital video network interface

A chip selection enable apparatus which outputs one of plural chip enable signals in correspondence to which of plural address signals appear on an address bus. The chip selection apparatus includes a programmable array logic device, connectable to the address bus, which is programmed to output at least one chip enable signal in response to address signals on the address bus, and which is also programmed to output N (N&gt;1) coded signals in response to other address signals on the address bus. A decoder is connected to the programmable array logic device and decodes the N coded signals into at least N+1 chip enable signals. In one preferred embodiment, the programmable array logic device is configured to output five chip enable signals and three coded signals. A standard one-of-eight binary decoder decodes the three coded signals into eight additional chip enable signals, thereby providing 13 chip enable signals from a single programmable array logic device, even though the programmable array logic device is capable of outputting only eight outputs.

System for generating chip select signals based on coded and uncoded

A network communication device has plural different connectors, each connectable to a network, and is capable of automatically selecting between the different connectors for network communication. A selector responsive to a selection signal selects one of the plural connectors, and a plurality of detectors, each associated with a corresponding connector, detects whether its corresponding connector is connected to the network. A processor executes a selection process by outputting a selection signal so as to select, in turn, each of the plural different connectors starting with a first connector, maintaining the state of the selection signal in a case where the detector associated with the selected connector indicates connection to the network, cycling to the next connector in a case where the detector does not indicate connection to the network, and repeating the selection process in a case where said processor has cycled through all of said plural connectors.

Automatic detection of network hardware connection

Method and apparatus for interfacing a printer to a local area network includes the use of an interactive network board coupling the printer to the LAN. A bi-directional printer interface is disposed on the board and transmits print data to the printer, and receives printer status data from the printer. ALAN interface is disposed on the board for receiving print job information and printer status requests from the LAN, and for transmitting printer status information to the LAN. A ROM is disposed on the board and stores (i) application programs which receive the print job information and transmit the print data to the printer, and (ii) status and control programs which receive the printer status requests from the LAN, receive printer status data from the printer, transmit the printer status information to the LAN, and receive control information from the LAN and transmit it to the printer. A processor disposed on the board executes both the application programs and the status and control programs. Preferably, the application programs are selectively capable of placing the network board into a plurality of different printer configurations.

Method and apparatus for interfacing a peripheral to a local area network

A serial port which transmits a start bit of a serial transmission to a non-maskable interrupt terminal of a microprocessor so as to be certain that the microprocessor responds to serial communication. The serial port includes a microprocessor-writable transmit bit connected to the transmit terminal of the serial port, a microprocessor-readable receive bit connected to the receive terminal of the serial port, and an NMI enable switch connected between the receive terminal and the NMI pin of the microprocessor. In a receive mode, the NMI enable switch which initially is in a conductive state, transmits the start bit of serial transmissions directly to the NMI pin of the microprocessor causing the microprocessor to interrupt on-going processes. The microprocessor disables the NMI enable register and, after waiting for serial transmission periods between transmitted bits, reads all eight data bits received at the receive terminal from the received bit. Thereafter, the microprocessor re-enables the NMI enable switch and resumes the suspended on-going processes. In a transmit mode, the microprocessor writes a binary 1, corresponding to a start bit, to the transmit bit, causing a transmit signal to be output from the transmit terminal. The microprocessor then transmits the eight bits corresponding to the desired transmit byte, each bit being separated by the appropriate inter-bit serial communication time interval.

Serial port using non-maskable interrupt terminal of a microprocessor

Apparatus for providing shared access to a shared RAM in situations where the shared RAM is electrically connected to a relatively slow address/data bus, and shared access is desired from a relatively faster address bus and data bus. An address buffer is connected between the address bus and the address/data bus, the address buffer for selectably buffering address information between those buses under control of an address buffer selection signal. A data buffer is connected between the data bus and the address/data bus, the data buffer for selectably buffering data information between those buses under control of a data buffer selection signal. A gate array is connected to the address/data bus, the gate array controlling access the shared RAM. A logic array is connected to the address bus and is responsive to address information on the address bus which corresponds to addresses of the shared RAM. In response to those addresses, the logic array activates the address buffer selection signal so as to cause the address buffer to buffer address information from the address bus onto the address/data bus, and thereafter by deactivating the address buffer selection signal and activating the data buffer selection signal so as to cause the data buffer to buffer data information from or to the address/data bus.

Shared RAM access arrangement

Method and apparatus for loading a ROM image into PROM comprises loading a ROM image into a dynamic random access memory, verifying the accuracy of the ROM image in the dynamic random access memory, and receiving a command to flash EPROM with the stored ROM image. A hardware interlock mechanism is deactivated by a two-step command procedure so as to enable flashing the EPROM. Specifically, a predetermined bit pattern is written to a first predetermined address on an address bus, one bit being latched to cause a flash signal to be output to a transistor switch and to be pre-loaded at a flip flop. A second predetermined address is read from so as to clock the flip flop. The output of the flip flop closes the transistor switch allowing the flash enable signal to reach the EPROM. The EPROM is erased, after which the ROM image is loaded into the PROM.

In an interactive network board, a method and apparatus for preventing

Method and apparatus for converting image data from row format into column format and a printer incorporating the same. A conversion circuit, which is responsive to writes to a first address space, is provided for converting the image data from the row format into the column format. A CPU writes the row format image data to the first address space whereupon the conversion circuit converts it to the second format. The CPU then writes image data to a second address space. In accordance with an unwind flag set by the CPU, either the converted image data or the original image data is stored in a memory. After the data has been written to memory, the CPU initiates a DMA transfer of the image data to a printer engine.

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Trabuco Canyon, CA, United States of America

Tony K Ip